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11. 发明申请

US20110278645A1 STRAIN-DIRECT-ON-INSULATOR (SDOI) SUBSTRATE AND METHOD OF FORMING 审中-公开
标题翻译：应变直接绝缘体（SDOI）基板和形成方法
公开(公告)号：US20110278645A1
公开(公告)日：2011-11-17
申请号：US13191288
申请日：2011-07-26
申请人： Lee Wee Teo , Chung Foong Tan , Shyue Seng Tan , Elgin Quek
发明人： Lee Wee Teo , Chung Foong Tan , Shyue Seng Tan , Elgin Quek
IPC分类号： H01L29/165
CPC分类号： H01L29/165 , H01L21/76254 , H01L29/1054 , Y10S438/933
摘要： Methods (and semiconductor substrates produced therefrom) of fabricating (n−1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed adjacent an outermost strained silicon layer. The outermost strained silicon layer and underlying relaxed SiGe layer is transferred to a handle substrate by conventional or known bonding and separation methods. The handle substrate is processed to remove the relaxed SiGe layer thereby producing an SDOI substrate for further use. The remaining donor substrate is processed to remove one or more layers to expose another strained silicon layer. Various processing steps are repeated to produce another SDOI substrate as well as a remaining donor substrate, and the steps may be repeated to produce n−1 SDOI substrates.
摘要翻译：描述了使用n个晶片制造（n-1）个SDOI衬底的方法（以及由此制备的半导体衬底）。施主衬底（例如，硅）包括缓冲层（例如，SiGe）和形成在其上的多个交替应力（例如，弛豫SiGe）和应变（例如硅）层的多层叠层。绝缘体邻近最外层应变硅层设置。最外层的应变硅层和下面的松弛的SiGe层通过常规或已知的粘结和分离方法转移到处理衬底。处理手柄基板以去除松弛的SiGe层，从而产生用于进一步使用的SDOI基板。处理剩余的施主衬底以除去一层或多层以暴露另一应变硅层。重复各种处理步骤以产生另一个SDOI衬底以及剩余的施主衬底，并且可以重复该步骤以产生n-1个SDOI衬底。

12. 发明申请

US20090179226A1 Strain-direct-on-insulator (SDOI) substrate and method of forming 有权
标题翻译：绝缘体绝缘体（SDOI）基板及其成型方法
公开(公告)号：US20090179226A1
公开(公告)日：2009-07-16
申请号：US12008841
申请日：2008-01-15
申请人： Lee Wee Teo , Chung Foong Tan , Shyue Seng Tan , Elgin Quek
发明人： Lee Wee Teo , Chung Foong Tan , Shyue Seng Tan , Elgin Quek
IPC分类号： H01L21/30 , H01L29/12
CPC分类号： H01L29/165 , H01L21/76254 , H01L29/1054 , Y10S438/933
摘要： Methods (and semiconductor substrates produced therefrom) of fabricating (n−1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed adjacent an outermost strained silicon layer. The outermost strained silicon layer and underlying relaxed SiGe layer is transferred to a handle substrate by conventional or known bonding and separation methods. The handle substrate is processed to remove the relaxed SiGe layer thereby producing an SDOI substrate for further use. The remaining donor substrate is processed to remove one or more layers to expose another strained silicon layer. Various processing steps are repeated to produce another SDOI substrate as well as a remaining donor substrate, and the steps may be repeated to produce n−1 SDOI substrates.
摘要翻译：描述了使用n个晶片制造（n-1）个SDOI衬底的方法（以及由此制备的半导体衬底）。施主衬底（例如，硅）包括缓冲层（例如，SiGe）和形成在其上的多个交替应力（例如，弛豫SiGe）和应变（例如硅）层的多层叠层。绝缘体邻近最外层应变硅层设置。最外层的应变硅层和下面的松弛的SiGe层通过常规或已知的粘结和分离方法转移到处理衬底。处理手柄基板以去除松弛的SiGe层，从而产生用于进一步使用的SDOI基板。处理剩余的施主衬底以除去一层或多层以暴露另一应变硅层。重复各种处理步骤以产生另一个SDOI衬底以及剩余的施主衬底，并且可以重复该步骤以产生n-1个SDOI衬底。

13. 发明授权

US08999863B2 Stress liner for stress engineering 有权
标题翻译：应力工程应力衬
公开(公告)号：US08999863B2
公开(公告)日：2015-04-07
申请号：US12133375
申请日：2008-06-05
申请人： Jae Gon Lee , Jingze Tian , Shyue Seng Tan , Luona Goh , Wei Lu , Elgin Quek
发明人： Jae Gon Lee , Jingze Tian , Shyue Seng Tan , Luona Goh , Wei Lu , Elgin Quek
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/78 , H01L29/66
CPC分类号： H01L21/823807 , H01L29/665 , H01L29/7843
摘要： A stress liner having first and second stress type is provided over a first type and a second type transistor to improve reliability and performance without incurring area penalties or layout deficiencies.
摘要翻译：具有第一和第二应力类型的应力衬垫设置在第一类型和第二类型晶体管上，以提高可靠性和性能，而不会引起区域损失或布局缺陷。

14. 发明授权

US07935589B2 Enhanced stress for transistors 有权
标题翻译：晶体管增强应力
公开(公告)号：US07935589B2
公开(公告)日：2011-05-03
申请号：US12111214
申请日：2008-04-29
申请人： Lee Wee Teo , Jae Gon Lee , Shyue Seng Tan , Elgin Quek
发明人： Lee Wee Teo , Jae Gon Lee , Shyue Seng Tan , Elgin Quek
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： A transistor disposed on a substrate includes a gate, spacers on gate sidewalls, and diffusion regions adjacent to the gate. Silicide contacts on the diffusion regions are displaced from the spacers by a distance G. Stressors may be provided in the diffusion region to induce a first stress in the channel region of the transistor.
摘要翻译：设置在基板上的晶体管包括栅极，栅极侧壁上的间隔物和与栅极相邻的扩散区域。扩散区上的硅化物接触从间隔物移位距离G。可以在扩散区域中提供应激源以在晶体管的沟道区域中引起第一应力。

15. 发明授权

US08748271B2 LDMOS with improved breakdown voltage 有权
标题翻译： LDMOS具有改善的击穿电压
公开(公告)号：US08748271B2
公开(公告)日：2014-06-10
申请号：US13046313
申请日：2011-03-11
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
IPC分类号： H01L29/772 , H01L29/40 , H01L29/49 , H01L29/78 , H01L29/51 , H01L29/66 , H01L29/423
CPC分类号： H01L29/7816 , H01L29/402 , H01L29/42368 , H01L29/495 , H01L29/4983 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66681
摘要： An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.
摘要翻译： LDMOS在n-漂移区上形成有与栅叠层共面的场板，并且具有比栅叠层更高的功函数。实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二共面栅叠层，分别调整第一和第二栅极堆叠的功函数，以获得第二栅极堆叠的较高功函数。其他实施例包括在栅极氧化物层上形成高k金属栅极的第一栅极堆叠和场板的第二栅极堆叠，在公共栅极氧化物上形成具有不同栅电极材料的第一和第二栅极堆叠，以及形成栅极堆叠彼此分离并具有不同的栅极电介质材料。

16. 发明授权

US08492235B2 FinFET with stressors 有权
公开(公告)号：US08492235B2
公开(公告)日：2013-07-23
申请号：US12980375
申请日：2010-12-29
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/0649 , H01L29/0847 , H01L29/1037 , H01L29/1054 , H01L29/41783 , H01L29/66795 , H01L29/7848 , H01L29/7849
摘要： A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduced height variations across the wafer. The fin type transistor may also include a buried stressor and/or raised or embedded raised S/D stressors to cause a strain in the channel to improve carrier mobility.

17. 发明申请

US20120018815A1 Semiconductor device with reduced contact resistance and method of manufacturing thereof 有权
标题翻译：具有降低的接触电阻的半导体器件及其制造方法
公开(公告)号：US20120018815A1
公开(公告)日：2012-01-26
申请号：US12804487
申请日：2010-07-22
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Shiang Yang Ong , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Shiang Yang Ong , Elgin Quek
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/28556 , H01L21/324 , H01L29/0847 , H01L29/41725 , H01L29/66575
摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.
摘要翻译：制造半导体器件的方法（和半导体器件）提供具有降低的接触电阻（和串联电阻）的场效应晶体管（FET），以提高器件性能。在接触硅化物形成之后，在源极/漏极（S / D）区域中注入杂质，并且进行尖峰退火处理，其降低硅化物和S / D层的下部结区之间的界面的肖特基势垒高度（SBH） D区。这导致较低的接触电阻并且减小了硅化物半导体界面处的区域的厚度（和Rs）。

18. 发明授权

US08470700B2 Semiconductor device with reduced contact resistance and method of manufacturing thereof 有权
公开(公告)号：US08470700B2
公开(公告)日：2013-06-25
申请号：US12804487
申请日：2010-07-22
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Shiang Yang Ong , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Shiang Yang Ong , Elgin Quek
IPC分类号： H01L21/26
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/28556 , H01L21/324 , H01L29/0847 , H01L29/41725 , H01L29/66575
摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.

19. 发明申请

US20120228705A1 LDMOS WITH IMPROVED BREAKDOWN VOLTAGE 有权
标题翻译： LDMOS具有改进的断电电压
公开(公告)号：US20120228705A1
公开(公告)日：2012-09-13
申请号：US13046332
申请日：2011-03-11
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/42364 , H01L29/42368 , H01L29/42372 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66681
摘要： An LDMOS is formed with a second gate stack over the n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, the first and second gate stacks sharing a common gate electrode, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack with a first high-k dielectric and the second gate stack with a second high-k dielectric, and forming the first and second gate stacks with asymmetric dielectrics.
摘要翻译： LDMOS在n漂移区上形成有第二栅极堆叠，其具有与栅极堆叠相同的公共栅电极，并且具有比栅极堆叠更高的功函数。实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二栅极叠层，第二阱，第一和第二栅极堆叠共享公共栅极电极，并且调谐第一和第二栅极堆叠的功函数以获得用于第二栅极堆叠的较高功函数。其他实施例包括用第一高k电介质形成第一栅极堆叠，以及用第二高k电介质形成第二栅极堆叠，以及用不对称电介质形成第一和第二栅极堆叠。

20. 发明申请

US20120228695A1 LDMOS WITH IMPROVED BREAKDOWN VOLTAGE 有权
标题翻译： LDMOS具有改进的断电电压
公开(公告)号：US20120228695A1
公开(公告)日：2012-09-13
申请号：US13046313
申请日：2011-03-11
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/402 , H01L29/42368 , H01L29/495 , H01L29/4983 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66681
摘要： An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.
摘要翻译： LDMOS在n-漂移区上形成有与栅叠层共面的场板，并且具有比栅叠层更高的功函数。实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二共面栅叠层，分别调整第一和第二栅极堆叠的功函数，以获得第二栅极堆叠的较高功函数。其他实施例包括在栅极氧化物层上形成高k金属栅极的第一栅极堆叠和场板的第二栅极堆叠，在公共栅极氧化物上形成具有不同栅电极材料的第一和第二栅极堆叠，以及形成栅极堆叠彼此分离并具有不同的栅极电介质材料。

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