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11. 发明授权

US08896048B1 Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors 有权
标题翻译：间隔物形成后源侧注入的装置和方法，以减少金属氧化物半导体场效应晶体管的短沟道效应
公开(公告)号：US08896048B1
公开(公告)日：2014-11-25
申请号：US10861581
申请日：2004-06-04
申请人： Richard Fastow , Zhigang Wang , Yue-Song He , Kazuhiro Mizutani , Pavel Fastenko
发明人： Richard Fastow , Zhigang Wang , Yue-Song He , Kazuhiro Mizutani , Pavel Fastenko
IPC分类号： H01L29/76
CPC分类号： H01L29/66659 , H01L29/66825 , H01L29/7881
摘要： The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.
摘要翻译：本发明提供一种制造用于减少短沟道效应的金属氧化物半导体场效应晶体管（MOSFET）的装置和方法。 MOSFET包括半导体衬底，形成在半导体衬底上方的栅极堆叠，形成在栅极堆叠的漏极侧的漏极侧壁间隔物，形成在栅极堆叠的源极侧的源极侧壁隔离物，以及源极和漏极地区。源极区域形成在源极侧的半导体衬底中，并且通过源极侧壁间隔物对齐以在源极区域和漏极区域之间延伸有效沟道长度。漏极区域形成在半导体衬底的漏极侧，并且通过漏极侧壁间隔物排列以进一步延长有效沟道长度。

12. 发明授权

US08125020B2 Non-volatile memory devices with charge storage regions 有权
标题翻译：具有电荷存储区域的非易失性存储器件
公开(公告)号：US08125020B2
公开(公告)日：2012-02-28
申请号：US11872477
申请日：2007-10-15
申请人： Yue-Song He , Len Mei
发明人： Yue-Song He , Len Mei
IPC分类号： H01L29/792 , H01L29/788
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/513 , H01L29/6656 , H01L29/66659 , H01L29/66833
摘要： A memory device includes a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, and a control gate. Applying a positive bias to the control gate, the select gate and the source of the device injects negative charges from a channel region of a substrate by hot electron injection through the tunneling dielectric layer at a location near a gap between the select gate and the control gate into the charge storage layer to store negative charges in the charge storage layer. Applying a negative bias to the control gate directly tunnels positive charges from the channel region of the substrate through the tunneling dielectric layer and into the charge storage layer to store positive charges in the charge storage layer.
摘要翻译：存储器件包括与电池堆相邻形成的电池堆和选择栅。电池堆包括隧道介电层，电荷存储层，阻挡介质层和控制栅极。对控制栅极施加正偏压，器件的选择栅极和源极通过在选择栅极和控制器之间的间隙附近的位置处的隧道电介质层通过热电子注入从衬底的沟道区域注入负电荷门进入电荷存储层以在电荷存储层中存储负电荷。将负偏压施加到控制栅极直接从衬底的沟道区通过隧道电介质层引导正电荷并进入电荷存储层，以在电荷存储层中存储正电荷。

13. 发明申请

US20090321806A1 NONVOLATILE MEMORY WITH FLOATING GATES WITH UPWARD PROTRUSIONS 审中-公开
标题翻译：具有浮动门的非易失性存储器具有上升的推移
公开(公告)号：US20090321806A1
公开(公告)日：2009-12-31
申请号：US12146933
申请日：2008-06-26
申请人： Len Mei , Yue-Song He
发明人： Len Mei , Yue-Song He
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/28114
摘要： Substrate isolation regions (570) initially protrude upward above a semiconductor substrate (520) but are later etched down. Before they are etched down, floating gate layer (590) is deposited and etched or polished off the top surfaces of the substrate isolation regions. The floating gate layer thus has upward protrusions overlying sidewalls of the substrate isolation regions. When the substrate isolation regions are etched down, the floating gate layer's upward protrusions' outer sidewalls become exposed. The upward protrusions serve to increase the capacitance between the floating and control gates. The floating gates' bottom surfaces are restricted to the active areas (564) not to overlie the substrate isolation regions. Other features are also provided.
摘要翻译：衬底隔离区（570）最初在半导体衬底（520）上方向上突出，但是后来被刻蚀掉。在蚀刻之前，浮栅层（590）被沉积并蚀刻或抛光离开衬底隔离区域的顶表面。因此，浮栅层具有覆盖衬底隔离区的侧壁的向上突起。当衬底隔离区被蚀刻时，浮栅层的向上突起的外侧壁变得暴露。向上的凸起用于增加浮动和控制门之间的电容。浮动栅极的底表面限于不覆盖衬底隔离区的有源区（564）。还提供其他功能。

14. 发明申请

US20090096013A1 NON-VOLATILE MEMORY DEVICES WITH CHARGE STORAGE REGIONS 有权
标题翻译：具有充电存储区域的非易失性存储器件
公开(公告)号：US20090096013A1
公开(公告)日：2009-04-16
申请号：US11872477
申请日：2007-10-15
申请人： Yue-Song He , Len Mei
发明人： Yue-Song He , Len Mei
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/513 , H01L29/6656 , H01L29/66659 , H01L29/66833
摘要： A memory device includes a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, and a control gate. Applying a positive bias to the control gate, the select gate and the source of the device injects negative charges from a channel region of a substrate by hot electron injection through the tunneling dielectric layer at a location near a gap between the select gate and the control gate into the charge storage layer to store negative charges in the charge storage layer. Applying a negative bias is to the control gates directly tunnels positive charges from the channel region of the substrate through the tunneling dielectric layer and into the charge storage layer to store positive charges in the charge storage layer.
摘要翻译：存储器件包括与电池堆相邻形成的电池堆和选择栅。电池堆包括隧道介电层，电荷存储层，阻挡介质层和控制栅极。对控制栅极施加正偏压，器件的选择栅极和源极通过在选择栅极和控制器之间的间隙附近的位置处的隧道电介质层通过热电子注入从衬底的沟道区域注入负电荷门进入电荷存储层以在电荷存储层中存储负电荷。施加负偏压是控制栅极直接从衬底的通道区域通过隧穿介电层隧穿正电荷并进入电荷存储层，以在电荷存储层中存储正电荷。

15. 发明授权

US07109555B1 Method for providing short channel effect control using a silicide VSS line 有权
标题翻译：使用硅化物VSS线提供短沟道效应控制的方法
公开(公告)号：US07109555B1
公开(公告)日：2006-09-19
申请号：US10835341
申请日：2004-04-28
申请人： Yue-Song He
发明人： Yue-Song He
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method for fabricating a semiconductor device having improved short channel effects is disclosed. The method includes operations such as, forming a hard mask layer on the surface of a semiconductor substrate, printing a photoresist mask above the hard mask layer, performing an etch of trenches in the semiconductor substrate and removing the hard mask layer and the photoresist mask. Moreover, the method includes forming a first polysilicon layer, etching the first polysilicon layer, forming a spacer layer and forming a second polysilicon layer. In addition, the method includes performing a stacked gate etch on the second polysilicon layer, performing an SAS etch, performing a shallow source implant and forming the spacer between the first polysilicon layer and the second polysilicon layer. A silicide line is subsequently formed to connect device source regions.
摘要翻译：公开了一种制造具有改善的短通道效应的半导体器件的方法。该方法包括在半导体衬底的表面上形成硬掩模层，在硬掩模层上印刷光致抗蚀剂掩模，对半导体衬底中的沟槽进行蚀刻并去除硬掩模层和光刻胶掩模的操作。此外，该方法包括形成第一多晶硅层，蚀刻第一多晶硅层，形成间隔层并形成第二多晶硅层。此外，该方法包括在第二多晶硅层上执行层叠栅极蚀刻，执行SAS蚀刻，执行浅源极注入并在第一多晶硅层和第二多晶硅层之间形成间隔物。随后形成硅化物线以连接器件源极区域。

16. 发明授权

US06867119B2 Nitrogen oxidation to reduce encroachment 有权
标题翻译：氮氧化减少侵蚀
公开(公告)号：US06867119B2
公开(公告)日：2005-03-15
申请号：US10284866
申请日：2002-10-30
申请人： Yue-Song He , Richard M. Fastow , Zhi-Gang Wang
发明人： Yue-Song He , Richard M. Fastow , Zhi-Gang Wang
IPC分类号： H01L21/28 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66825 , H01L21/28247 , H01L21/28273
摘要： A method of manufacturing a metal oxide semiconductor. A gate structure of the metal oxide semiconductor is etched. A nitrogen-comprising gas, which may be NO or N2O, is made to flow over the metal oxide semiconductor. A pre-implant film is grown over the edges of the gate structure. The pre-implant film may repair damage to a gate stack edge caused by an etching process. The film may be substantially silicon nitride. Beneficially, such a film may be thinner than a conventional silica oxide film. A thinner film does not deleteriously contribute to non-uniformities in a tunnel oxide. A non-uniform tunnel oxide may result in a non-uniform field between a gate and a channel. Non-uniform fields may have numerous deleterious effects. Advantageously, embodiments of the present invention overcome prior art deficiencies in repairing gate stack edge defects. In this novel manner, gate stack edge defects may be physically repaired without deleterious consequences to the electrical behavior of a metal oxide semiconductor device. The novel application of silicon nitride to this application allows thin repair layers to be grown. Advantageously, semiconductors manufactured using embodiments of the present invention may utilize smaller process feature sizes, resulting in denser arrays of semiconductor devices, resulting in lower costs for such devices and realizing a competitive advantage to practitioners of the improvements in the arts herein described.
摘要翻译：一种制造金属氧化物半导体的方法。蚀刻金属氧化物半导体的栅极结构。使含氮气体（可以是NO或N 2 O）流过金属氧化物半导体。在门结构的边缘上生长预植入膜。预植入膜可以修复由蚀刻工艺引起的栅堆叠边缘的损坏。该膜可以基本上是氮化硅。有利地，这种膜可以比常规二氧化硅膜薄。更薄的膜对隧道氧化物中的不均匀性没有有害的贡献。不均匀隧道氧化物可能导致栅极和沟道之间的不均匀场。非均匀场可能有许多有害影响。有利地，本发明的实施例克服了修复栅极堆叠边缘缺陷的现有技术缺陷。以这种新颖的方式，可以物理地修复栅极堆叠边缘缺陷，而不会对金属氧化物半导体器件的电气行为产生有害影响。氮化硅在该应用中的新颖应用允许生长薄的修复层。有利地，使用本发明的实施例制造的半导体可以利用较小的工艺特征尺寸，导致更密集的半导体器件阵列，从而导致这些器件的成本降低，并且对于本领域技术人员的改进实现了竞争优势。

17. 发明授权

US06580639B1 Method of reducing program disturbs in NAND type flash memory devices 有权
标题翻译：减少NAND型闪存器件编程干扰的方法
公开(公告)号：US06580639B1
公开(公告)日：2003-06-17
申请号：US09372406
申请日：1999-08-10
申请人： Yue-Song He , Kent Kuohua Chang , Allen U. Huang
发明人： Yue-Song He , Kent Kuohua Chang , Allen U. Huang
IPC分类号： G11C1604
CPC分类号： H01L29/66575 , G11C16/0483 , H01L21/26506 , H01L21/26513 , H01L29/66825 , H01L29/66833 , H01L29/78
摘要： The present invention makes use of ion bombardment to amorphize the source and drain regions of a short channel FET prior to implanting. The source/drain implants are then localized to a shallow depth by appropriate choice of implanting conditions, typically employing rather low bombardment voltages of approximately 10 KeV. Amorphous source/drain regions substantially hinder the diffusion of source/drain dopants and thereby reduce the possibility of punchthrough and loss of FET function. Such devices are preferably used in NAND type flash memory devices maintaining proper self-boosting voltages and FET functions even when short channel lengths are employed.
摘要翻译：本发明利用离子轰击在植入之前使短沟道FET的源极和漏极区域非晶化。然后通过适当选择植入条件将源极/漏极植入物定位到浅深度，通常采用约10KeV的相当低的轰击电压。无定形源极/漏极区域基本上阻碍了源极/漏极掺杂剂的扩散，从而降低了FET功能的穿透和损失的可能性。这种器件优选地用于NAND型闪速存储器件中，即使采用短沟道长度，它们也保持适当的自增强电压和FET功能。

18. 发明申请

US20110309421A1 ONE-TIME PROGRAMMABLE MEMORY AND METHOD FOR MAKING THE SAME 有权
标题翻译：一次可编程存储器及其制造方法
公开(公告)号：US20110309421A1
公开(公告)日：2011-12-22
申请号：US12819566
申请日：2010-06-21
申请人： Harry S. Luan , Yue-Song He , Ting-Wah Wong
发明人： Harry S. Luan , Yue-Song He , Ting-Wah Wong
IPC分类号： H01L27/105 , H01L29/78 , H01L23/525
CPC分类号： H01L27/112 , G11C17/16 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate.
摘要翻译：由金属绝缘体半导体电池形成的一次可编程非易失性存储器。电池处于形成在半导体衬底中的导电栅极线和交叉掺杂半导体线的交叉点。

19. 发明申请

US20090256221A1 METHOD FOR MAKING VERY SMALL ISOLATED DOTS ON SUBSTRATES 审中-公开
标题翻译：在基材上制造非常小的分离物的方法
公开(公告)号：US20090256221A1
公开(公告)日：2009-10-15
申请号：US12101908
申请日：2008-04-11
申请人： Len Mei , Yue-Song He
发明人： Len Mei , Yue-Song He
IPC分类号： H01L29/82 , H01L21/306
CPC分类号： H01L21/32139 , B82Y10/00 , B82Y25/00 , H01L21/0337 , H01L21/0338 , H01L27/222
摘要： A method for forming very small isolated dots of a target material, e.g., a ferromagnetic material or phase change material, on a substrate includes providing a substrate having a layer of the target material disposed on a surface thereof, etching the layer of target material so as to form a plurality of lines of the material on the surface of the substrate, and etching the lines of the target material so as to form a rectangular matrix of substantially similar, very small isolated dots of the target material on the substrate. By the successive formation of orthogonally intersecting linear patterns on the substrate, including the formation and use of “hard” etch masks, spacer approach and selective etching techniques, the method enables very small (
摘要翻译：在衬底上形成目标材料（例如铁磁材料或相变材料）的非常小的孤立点的方法包括提供具有设置在其表面上的目标材料层的衬底，蚀刻靶材料层以在衬底的表面上形成多条材料线，并蚀刻目标材料的线以便形成基板上目标材料基本相似的非常小的孤立点的矩形矩阵。通过在衬底上连续形成正交相交的线性图案，包括形成和使用“硬”蚀刻掩模，间隔法和选择性蚀刻技术，该方法使目标材料的非常小的（<65nm）孤立点为通过使用常规的193nm波长光刻方法和装置可靠地形成在基板上。

20. 发明申请

US20090251972A1 NONVOLATILE MEMORY ARRAYS WITH CHARGE TRAPPING DIELECTRIC AND WITH NON-DIELECTRIC NANODOTS 审中-公开
标题翻译：带电荷捕捉电介质和非电介质纳米片的非易失性存储器阵列
公开(公告)号：US20090251972A1
公开(公告)日：2009-10-08
申请号：US12062037
申请日：2008-04-03
申请人： Yue-Song He , Len Mei
发明人： Yue-Song He , Len Mei
IPC分类号： G11C16/04 , H01L21/336 , H01L29/792
CPC分类号： H01L29/66833 , H01L29/42344 , H01L29/792
摘要： Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.
摘要翻译：非易失性存储单元中的电荷俘获电介质（160）从控制栅极的边缘和/或从衬底隔离区域的边缘凹陷。凹入的几何形状用于减少或消除电荷难以擦除的区域中的电荷捕获。

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