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11. 发明授权

US08144625B2 DisplayPort auxiliary channel active buffer with auxiliary channel/display data channel combiner for fast auxiliary channel 有权
标题翻译： DisplayPort辅助通道主动缓冲器，辅助通道/显示数据通道组合器，用于快速辅助通道
公开(公告)号：US08144625B2
公开(公告)日：2012-03-27
申请号：US12643759
申请日：2009-12-21
申请人： Ming Qu , Zhengyu Yuan , Kochung Lee
发明人： Ming Qu , Zhengyu Yuan , Kochung Lee
IPC分类号： H04L12/28 , H04L1/00 , H04L12/26 , H03K5/01 , G06F13/00
CPC分类号： G06F3/14 , G09G5/003 , G09G5/363 , G09G2370/047 , G09G2370/12 , H04L43/16
摘要： A system and a method for exchanging communication data between devices using a bi-directional communication channel are disclosed. A combiner is coupled to a source device via first bi-directional configuration channel and to a sink device via a second bi-directional configuration channel. Upon receiving data from the first bi-directional configuration channel and not receiving data from the second bi-directional configuration channel, the combiner transmits the received data to the sink device using the second bi-directional configuration channel and prevents data transmission from the sink device to the source device using the second bi-directional configuration channel. Similarly, upon receiving data from the second bi-directional configuration channel and not receiving from the first bi-directional configuration channel, the combiner prevents data transmission from the source device to the sink device and transmits the received data to the source device using the first bi-directional configuration channel.
摘要翻译：公开了一种使用双向通信信道在设备之间交换通信数据的系统和方法。组合器经由第一双向配置信道耦合到源设备，并经由第二双向配置信道耦合到宿设备。在从第一双向配置信道接收数据并且没有从第二双向配置信道接收数据时，组合器使用第二双向配置信道将接收的数据发送到宿设备，并且防止从宿设备的数据传输使用第二双向配置信道到源设备。类似地，当从第二双向配置信道接收到数据并且没有从第一双向配置信道接收时，组合器防止从源设备到宿设备的数据传输，并且使用第一双向配置信道将接收到的数据发送到源设备双向配置通道。

12. 发明申请

US20050264321A1 Current mode logic buffer 有权
标题翻译：电流模式逻辑缓冲器
公开(公告)号：US20050264321A1
公开(公告)日：2005-12-01
申请号：US10856100
申请日：2004-05-28
申请人： Kochung Lee
发明人： Kochung Lee
IPC分类号： H03K19/0175 , H03K19/0185
CPC分类号： H03K19/018528
摘要： Systems and methods provide current mode logic buffers and interface circuits. As an example, in accordance with an embodiment of the present invention, a CML buffer is disclosed that receives and/or provides multiple signal pairs having different common mode voltages to operate over a wider common mode voltage range.
摘要翻译：系统和方法提供电流模式逻辑缓冲器和接口电路。作为示例，根据本发明的实施例，公开了一种CML缓冲器，其接收和/或提供具有不同共模电压的多个信号对以在更宽的共模电压范围内工作。

13. 发明授权

US06680625B1 Symmetrical CML logic gate system 失效
标题翻译：对称CML逻辑门系统
公开(公告)号：US06680625B1
公开(公告)日：2004-01-20
申请号：US10066031
申请日：2002-01-31
申请人： Kochung Lee , Ming Qu , Xueping Jiang , Xiang Zhu
发明人： Kochung Lee , Ming Qu , Xueping Jiang , Xiang Zhu
IPC分类号： H03K1920
CPC分类号： H03K19/215 , H03K19/1738
摘要： High speed CML logic gate systems for providing selected Boolean logic functions. Two halves of a substantially symmetric first system, having a relatively small number (14) of CMOS transistors, are used to generate any of the logic functions AND, NAND, OR and NOR. Two halves of a substantially symmetric second system having another small number (10) of transistors are used to generate any of the logic functions XOR, XNOR and NOT. In either system, the sum of currents passing through certain voltage-controlling gates is substantially constant.
摘要翻译：用于提供所选布尔逻辑功能的高速CML逻辑门系统。使用具有相对较小数量（14）的CMOS晶体管的基本上对称的第一系统的两半用于产生逻辑功能AND，NAND，OR和NOR中的任一个。使用具有另外少数（10）个晶体管的基本上对称的第二系统的两半来产生任何逻辑函数XOR，XNOR和NOT。在任一系统中，通过某些电压控制门的电流之和基本上是恒定的。

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