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11. 发明授权

US06785322B1 Node-B/base station rake finger pooling 失效
标题翻译：节点B /基站耙指池
公开(公告)号：US06785322B1
公开(公告)日：2004-08-31
申请号：US10331085
申请日：2002-12-27
申请人： John David Kaewell, Jr. , Timothy Berghuis , Jan Meyer , Peter Bohnhoff , Alexander Reznik , Edward Hepler , Michael Koch , William C. Hackett , David S. Bass , Clyde N. Robbins
发明人： John David Kaewell, Jr. , Timothy Berghuis , Jan Meyer , Peter Bohnhoff , Alexander Reznik , Edward Hepler , Michael Koch , William C. Hackett , David S. Bass , Clyde N. Robbins
IPC分类号： H04B1707
CPC分类号： H04B1/712 , H04B1/7117 , H04B7/0491 , H04B2201/7071 , H04B2201/70711
摘要： A Node-B/base station receiver comprises at least one antenna for receiving signals. Each finger of a pool of reconfigurable Rake fingers recovers a multipath component of a user and is assigned a code of the user, a code phase of the multipath component and an antenna of the at least one antenna. An antenna/Rake finger pool interface provides each finger of the Rake pool an output of the antenna assigned to that Rake finger. A combiner combines the recovered multipath components for a user to produce data of the user.
摘要翻译：节点B /基站接收机包括用于接收信号的至少一个天线。可重构Rake指针池的每个手指恢复用户的多径分量，并且被分配用户的代码，多径分量的码相位和至少一个天线的天线。天线/耙指池接口为耙池的每个手指提供分配给该耙指的天线的输出。组合器将用于用户的恢复的多路径组件组合以产生用户的数据。

12. 发明授权

US07908545B2 Pipeline architecture for maximum a posteriori (MAP) decoders 失效
标题翻译：最大后验（MAP）解码器的管道架构
公开(公告)号：US07908545B2
公开(公告)日：2011-03-15
申请号：US11653014
申请日：2007-01-12
申请人： Edward Hepler , Michael F. Starsinic
发明人： Edward Hepler , Michael F. Starsinic
IPC分类号： H03M13/03
CPC分类号： H03M13/3905 , H03M13/3972 , H03M13/6505
摘要： The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for the first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is written to the same memory location. The calculations can be reversed, reverse metrics being calculated first, followed by reverse metric calculations. Although this architecture as developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.
摘要翻译：流水线最大后验（MAP）解码器架构的滑动窗口方法被修改以减少处理时间。一旦为解码器的第一滑动窗口计算了前向量度，则在计算下一窗口的前向量度时，计算每个窗口的反向度量。当每个新的前向度量被计算并存储到存储器中时，从存储器中读取来自前一窗口的前向度量用于在计算外在值时计算的反向度量。用于计算外在值的每个前向量度被写入同一个存储单元。计算可以反转，首先计算反向度量，然后是反向度量计算。虽然为turbo解码器开发的这种架构，但是所有的卷积码都可以使用本发明的MAP算法。

13. 发明申请

US20080016287A1 SYMBOL RATE HARDWARE ACCELERATOR 有权
标题翻译：符号速率硬件加速器
公开(公告)号：US20080016287A1
公开(公告)日：2008-01-17
申请号：US11776610
申请日：2007-07-12
申请人： Edward Hepler
发明人： Edward Hepler
IPC分类号： G06F12/02 , G06F11/10
CPC分类号： H04L1/0043 , H04L1/0065 , H04L1/0071
摘要： A hardware accelerator includes a first buffer, a second buffer, address generator(s), a translation read-only memory (ROM), a cyclic redundancy check (CRC) generator, a convolutional encoder and a controller. The first and second buffers store information bits. The address generator(s) generate(s) an address for accessing the first buffer, the second buffer and a shared memory architecture (SMA). The translation ROM is used in generating a translated address for accessing the first buffer and the second buffer. The controller sets parameters for the CRC generator, the convolutional encoder and the address generator, and performs a predefined sequence of control commands for channel processing, such as reordering, block coding, parity tailing, puncturing, convolutional encoding, and interleaving, on the information bits by manipulating the information bits while moving the information bits among the first buffer, the second buffer, the SMA, the CRC generator, and the convolutional encoder.
摘要翻译：硬件加速器包括第一缓冲器，第二缓冲器，地址生成器，转换只读存储器（ROM），循环冗余校验（CRC）发生器，卷积编码器和控制器。第一和第二缓冲器存储信息位。地址生成器生成用于访问第一缓冲器，第二缓冲器和共享存储器体系结构（SMA）的地址。翻译ROM用于生成用于访问第一缓冲器和第二缓冲器的翻译地址。控制器设置CRC发生器，卷积编码器和地址生成器的参数，并且对信息执行诸如重新排序，块编码，奇偶校验拖尾，删截，卷积编码和交织等信道处理的预定义的控制命令序列在第一缓冲器，第二缓冲器，SMA，CRC发生器和卷积编码器中移动信息位的同时操纵信息位。

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