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11. 发明授权

US07065628B2 Increasing memory access efficiency for packet applications 失效
公开(公告)号：US07065628B2
公开(公告)日：2006-06-20
申请号：US10158409
申请日：2002-05-29
申请人： Juan-Carlos Calderon , Jing Ling , Jean-Michel Caia , Vivek Joshi , Anguo T. Huang
发明人： Juan-Carlos Calderon , Jing Ling , Jean-Michel Caia , Vivek Joshi , Anguo T. Huang
IPC分类号： G06F12/00
CPC分类号： H04L49/103 , H04L49/109 , H04L49/254
摘要： Memory access efficiency for packet applications may be improved by transferring full partitions of data. The number of full partitions written to external memory may be increased by temporarily storing packets using on-chip memory that is on a chip with the processor. Before writing packets to external memory, packets of length smaller than the external memory partition size may be temporarily stored in the on-chip memory until an amount corresponding to a full or nearly full partition has been collected, at which point the data can be efficiently written to an external memory partition.

12. 发明授权

US06944728B2 Interleaving memory access 失效
标题翻译：交换内存访问
公开(公告)号：US06944728B2
公开(公告)日：2005-09-13
申请号：US10329283
申请日：2002-12-23
申请人： Juan-Carlos Calderon , Jean-Michel Caia , Vivek Joshi , Jing Ling , Anguo T. Huang
发明人： Juan-Carlos Calderon , Jean-Michel Caia , Vivek Joshi , Jing Ling , Anguo T. Huang
IPC分类号： G06F12/00 , H04L12/56
CPC分类号： H04L49/103
摘要： Interleaving memory access includes enabling data included in a receive flow of data to be stored in a first memory bank, enabling data included in a transmit flow of data to be stored in a second memory bank, and alternating access of data in the first memory bank with access of data in the second memory bank.
摘要翻译：交错存储器访问包括允许包含在接收数据流中的数据被存储在第一存储体中，使包含在数据传输流中的数据能够存储在第二存储体中，以及交替访问第一存储体中的数据具有访问第二存储体中的数据。

13. 发明授权

US07295564B2 Virtual output queue (VoQ) management method and apparatus 有权
标题翻译：虚拟输出队列（VoQ）管理方法和设备
公开(公告)号：US07295564B2
公开(公告)日：2007-11-13
申请号：US10337615
申请日：2003-01-06
申请人： Jing Ling , Juan-Carlos Calderon , Jean-Michel Caia , Anguo T. Huang , Vivek Joshi
发明人： Jing Ling , Juan-Carlos Calderon , Jean-Michel Caia , Anguo T. Huang , Vivek Joshi
IPC分类号： H04L12/54
CPC分类号： H04L49/3045 , H04L47/50 , H04L47/621 , H04L47/624 , H04L49/205 , H04L49/3027 , H04L49/3072 , H04L49/90 , H04L49/901 , H04L49/9094
摘要： A method and apparatus for providing a virtual output queue (VoQ) from a received set of data packets in a multi-service system. Each packet is divided into at least one partition, including a last partition that includes packet information, such as error status and packet length. The system receives the packet from a flow, parses the packet into partitions, including a first partition and the last partition, places each last partition into a linked list based on a time when the last partition was received, links the last partition to the first partition, and employs the linked list as the output queue. This system allows for rapid compilation and transmission of different sized packets, and obviates the need for the receiving processor to wait for the last partition to discard a bad packet.
摘要翻译：一种用于在多业务系统中从接收的一组数据分组提供虚拟输出队列（VoQ）的方法和装置。每个分组被分成至少一个分区，包括包括分组信息的最后一个分区，例如错误状态和分组长度。系统从流接收数据包，将数据包解析为分区，包括第一个分区和最后一个分区，根据接收到最后一个分区的时间，将最后一个分区放入链表中，将最后一个分区链接到第一个分区分区，并使用链表作为输出队列。该系统允许不同大小的分组的快速编译和传输，并且避免了接收处理器等待最后一个分区丢弃坏分组的需要。

14. 发明授权

US07154853B2 Rate policing algorithm for packet flows 有权
公开(公告)号：US07154853B2
公开(公告)日：2006-12-26
申请号：US10137753
申请日：2002-05-02
申请人： Jean-Michel Caia , Jing Ling , Juan-Carlos Calderon , Vivek Joshi , Anguo T. Huang
发明人： Jean-Michel Caia , Jing Ling , Juan-Carlos Calderon , Vivek Joshi , Anguo T. Huang
IPC分类号： G01R31/08 , G06F11/00
CPC分类号： H04L12/5601 , H04L2012/5636 , H04L2012/5637
摘要： A rate policing algorithm for packet flows is based on counters and threshold checking. The rate policing algorithm utilizes a state machine having four links: (1) compliant state to compliant state; (2) transition from compliant state to non-compliant state; (3) non-compliant state to non-compliant state; and (4) transition from non-compliant state to compliant state. Depending on the values obtained from the counters and utilizing the threshold values, it is determined whether a flow rate for packets is compliant or non-compliant.

15. 发明申请

US20060221944A1 Differential delay compensation 有权
公开(公告)号：US20060221944A1
公开(公告)日：2006-10-05
申请号：US11093907
申请日：2005-03-30
申请人： Jing Ling , Soowan Suh , Juan-Carlos Calderon
发明人： Jing Ling , Soowan Suh , Juan-Carlos Calderon
IPC分类号： H04L12/50
CPC分类号： G06F12/06 , H04J3/0623 , H04J2203/0094 , H04L45/742 , H04L49/30 , H04L49/90 , H04L49/901
摘要： In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.

16. 发明授权

US08488631B2 Differential delay compensation 有权
标题翻译：差分延时补偿
公开(公告)号：US08488631B2
公开(公告)日：2013-07-16
申请号：US13229455
申请日：2011-09-09
申请人： Jing Ling , Soowan Suh , Juan-Carlos Calderon
发明人： Jing Ling , Soowan Suh , Juan-Carlos Calderon
IPC分类号： H04J99/00
CPC分类号： G06F12/06 , H04J3/0623 , H04J2203/0094 , H04L45/742 , H04L49/30 , H04L49/90 , H04L49/901
摘要： In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.
摘要翻译：在一个实施例中，一种方法包括：接收表示至少一个虚拟级联数据流的多个数据帧，将多个数据帧存储在存储器中; 并且针对多个数据帧中的每一个记录指示存储器中的位置的物理写入地址和包括多帧指示符和字节数指示符的虚拟写入地址。

17. 发明授权

US07606269B1 Method and apparatus for detecting and managing loss of alignment in a virtually concatenated group 有权
标题翻译：用于检测和管理虚拟连接组中的对准损失的方法和装置
公开(公告)号：US07606269B1
公开(公告)日：2009-10-20
申请号：US10900813
申请日：2004-07-27
申请人： Soowan Suh , Jing Ling , Juan-Carlos Calderon , Rodrigo Gonzalez
发明人： Soowan Suh , Jing Ling , Juan-Carlos Calderon , Rodrigo Gonzalez
IPC分类号： H04J3/06 , H04L12/28 , H04L12/56
CPC分类号： H04J3/14 , H04J3/062 , H04J2203/006 , H04J2203/0094 , Y10S370/907
摘要： A method and apparatus for determining a loss of alignment defect in a communications network employing virtually concatenated payloads is provided. The method and apparatus comprise performing specific evaluations and assessments of conditions under normal conditions as well as evaluations and assessments under LCAS conditions where additional members may be added using the LCAS ADD state.
摘要翻译：提供了一种用于确定采用虚拟级联有效载荷的通信网络中的对准缺陷损失的方法和装置。方法和装置包括在正常条件下对条件进行具体评估和评估，以及在LCAS条件下进行评估和评估，其中可以使用LCAS ADD状态添加其他成员。

18. 发明申请

US20110317721A1 DIFFERENTIAL DELAY COMPENSATION 有权
标题翻译：差分延迟补偿
公开(公告)号：US20110317721A1
公开(公告)日：2011-12-29
申请号：US13229455
申请日：2011-09-09
申请人： Jing Ling , Soowan Suh , Juan-Carlos Calderon
发明人： Jing Ling , Soowan Suh , Juan-Carlos Calderon
IPC分类号： H04J99/00
CPC分类号： G06F12/06 , H04J3/0623 , H04J2203/0094 , H04L45/742 , H04L49/30 , H04L49/90 , H04L49/901
摘要： In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.
摘要翻译：在一个实施例中，一种方法包括：接收表示至少一个虚拟级联数据流的多个数据帧，将多个数据帧存储在存储器中; 并且针对多个数据帧中的每一个记录指示存储器中的位置的物理写入地址和包括多帧指示符和字节数指示符的虚拟写入地址。

19. 发明授权

US08018926B2 Differential delay compensation 有权
标题翻译：差分延时补偿
公开(公告)号：US08018926B2
公开(公告)日：2011-09-13
申请号：US11093907
申请日：2005-03-30
申请人： Jing Ling , Soowan Suh , Juan-Carlos Calderon
发明人： Jing Ling , Soowan Suh , Juan-Carlos Calderon
IPC分类号： H04L12/50
CPC分类号： G06F12/06 , H04J3/0623 , H04J2203/0094 , H04L45/742 , H04L49/30 , H04L49/90 , H04L49/901
摘要： In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.
摘要翻译：在一个实施例中，一种方法包括：接收表示至少一个虚拟级联数据流的多个数据帧，将多个数据帧存储在存储器中; 并且针对多个数据帧中的每一个记录指示存储器中的位置的物理写入地址和包括多帧指示符和字节数指示符的虚拟写入地址。

20. 发明申请

US20120269511A1 SIGNAL FORMAT CONVERSION APPARATUS AND METHODS 有权
标题翻译：信号格式转换装置和方法
公开(公告)号：US20120269511A1
公开(公告)日：2012-10-25
申请号：US13091908
申请日：2011-04-21
申请人： Juan-Carlos Calderon , Jean-Michel Caia , Arun Zarabi , Aws Shallal , Theron Paul Niederer
发明人： Juan-Carlos Calderon , Jean-Michel Caia , Arun Zarabi , Aws Shallal , Theron Paul Niederer
IPC分类号： H04J14/00
CPC分类号： H04J3/1664 , H04J2203/0089
摘要： Signal format conversion apparatus and methods involve converting data signals between a first signal format associated with a first reference clock rate and a second signal format that is different from the first signal format and is associated with a second reference clock rate different from the first reference clock rate. A period of the second signal format is changed to match a period of a third signal format by controlling a synchronized second reference clock rate that is applied in converting data signals between the first signal format and the second signal format. The synchronized second reference clock rate is different from the second reference clock rate and is synchronized with a third reference clock rate. The third reference clock rate is associated with the third signal format. Such synchronization simplifies conversion of signals between the second and third signal formats.
摘要翻译：信号格式转换装置和方法包括在与第一参考时钟速率相关联的第一信号格式和不同于第一信号格式的第二信号格式之间转换数据信号，并且与不同于第一参考时钟的第二参考时钟速率相关联率。通过控制在第一信号格式和第二信号格式之间转换数据信号中应用的同步的第二参考时钟速率来改变第二信号格式的周期以匹配第三信号格式的周期。同步的第二参考时钟速率与第二参考时钟速率不同，并且与第三参考时钟速率同步。第三参考时钟速率与第三信号格式相关联。这种同步简化了第二和第三信号格式之间信号的转换。

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