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11. 发明授权

US06851041B2 Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor 失效
标题翻译：用于动态超长指令字子指令选择的方法和装置，用于间接非常长的指令字处理器中的执行时间并行性
公开(公告)号：US06851041B2
公开(公告)日：2005-02-01
申请号：US10254012
申请日：2002-09-24
申请人： Gerald G. Pechanek , Juan Guillermo Revilla , Edwin Franklin Barry
发明人： Gerald G. Pechanek , Juan Guillermo Revilla , Edwin Franklin Barry
IPC分类号： G06F9/38 , G06F20060101 , G06F9/30 , G06F9/318 , G06F9/32 , G06F15/00 , G06F15/80
CPC分类号： G06F9/3842 , G06F9/3017 , G06F9/3822 , G06F9/3853
摘要： A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory for storing very-long-instruction-words (VLIWs) used in operations involving the execution of two or more functional units in parallel. Each VLIW comprises a plurality of short-instruction-words (SIWs) where each SIW corresponds to a unique type of instruction associated with a unique functional unit. VLIWs are composed in the VLIW memory by loading and concatenating SIWs in each address, or entry. VLIWs are executed via the execute-VLIW (XV) instruction. The iVLIWs can be compressed at a VLIW memory address by use of a mask field contained within the XV1 instruction which specifies which functional units are enabled, or disabled, during the execution of the VLIW. The mask can be changed each time the XV1 instruction is executed, effectively modifying the VLIW every time it is executed. The VLIW memory (VIM) can be further partitioned into separate memories each associated with a function decode-and-execute unit. With a second execute VLIW instruction XV2, each functional unit's VIM can be independently addressed thereby removing duplicate SIWs within the functional unit's VIM. This provides a further optimization of the VLIW storage thereby allowing the use of smaller VLIW memories in cost sensitive applications.
摘要翻译：流水线数据处理单元包括指令定序器和能够并行执行n个操作的n个功能单元。指令定序器包括用于存储在涉及并行执行两个或多个功能单元的操作中使用的非常长指令字（VLIW）的随机存取存储器。每个VLIW包括多个短指令字（SIW），其中每个SIW对应于与唯一功能单元相关联的唯一类型的指令。 VLIW通过在每个地址或条目中加载和连接SIW来组成VLIW存储器。 VLIW通过执行VLIW（XV）指令执行。通过使用XV1指令中包含的掩码字段，可以在VLIW存储器地址处压缩iVLIW，该掩码字段指定在执行VLIW期间启用或禁用哪些功能单元。每次执行XV1指令时，可以更改掩码，每次执行时都可以有效地修改VLIW。 VLIW存储器（VIM）可以被进一步划分成各自与功能解码和执行单元相关联的存储器。通过第二执行VLIW指令XV2，可以独立地对每个功能单元的VIM进行寻址，从而去除功能单元的VIM内的重复SIW。这提供了VLIW存储器的进一步优化，从而允许在成本敏感的应用中使用较小的VLIW存储器。

12. 发明授权

US6151668A Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication 有权
公开(公告)号：US6151668A
公开(公告)日：2000-11-21
申请号：US187539
申请日：1998-11-06
申请人： Gerald G. Pechanek , Thomas L. Drabenstott , Juan Guillermo Revilla , David Carl Strube , Grayson Morris
发明人： Gerald G. Pechanek , Thomas L. Drabenstott , Juan Guillermo Revilla , David Carl Strube , Grayson Morris
IPC分类号： G06F9/38 , G06F15/80 , G06F9/00
CPC分类号： G06F9/30145 , G06F9/30167 , G06F9/3802 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： A SIMD machine employing a plurality of parallel processor (PEs) in which communications hazards are eliminated in an efficient manner. An indirect Very Long Instruction Word instruction memory (VIM) is employed along with execute and delimiter instructions. A masking mechanism may be employed to control which PEs have their VIMs loaded. Further, a receive model of operation is preferably employed. In one aspect, each PE operates to control a switch that selects from which PE it receives. The present invention addresses a better machine organization for execution of parallel algorithms that reduces hardware cost and complexity while maintaining the best characteristics of both SIMD and MIMD machines and minimizing communication latency. This invention brings a level of MIMD computational autonomy to SIMD indirect Very Long Instruction Word (iVLIW) processing elements while maintaining the single thread of control used in the SIMD machine organization. Consequently, the term Synchronous-MIMD (SMIMD) is used to describe the present approach.

13. 发明授权

US06101592A Methods and apparatus for scalable instruction set architecture with dynamic compact instructions 有权
公开(公告)号：US06101592A
公开(公告)日：2000-08-08
申请号：US215081
申请日：1998-12-18
申请人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
发明人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F15/80
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30149 , G06F9/30178 , G06F9/30181 , G06F9/382 , G06F9/3885
摘要： A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs. In addition, the ManArray ISA is defined as a hierarchy of ISAs which allows for future growth in instruction capability and supports the packing of multiple instructions within a hierarchy of instructions.

14. 发明授权

US06775766B2 Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor 有权
标题翻译：用于动态重新配置间接非常长的指令字可缩放处理器的指令流水线的方法和装置
公开(公告)号：US06775766B2
公开(公告)日：2004-08-10
申请号：US09796040
申请日：2001-02-28
申请人： Juan Guillermo Revilla , Edwin F. Barry , Patrick Rene Marchand , Gerald G. Pechanek
发明人： Juan Guillermo Revilla , Edwin F. Barry , Patrick Rene Marchand , Gerald G. Pechanek
IPC分类号： G06F922
CPC分类号： G06F9/3873 , G06F9/30058 , G06F9/30076 , G06F9/30079 , G06F9/30181 , G06F9/30189 , G06F9/3802 , G06F9/3842 , G06F9/3853 , G06F9/3859 , G06F9/3867 , G06F9/3885
摘要： A ManArray processor pipeline design addresses an indirect VLIW memory access problem without increasing branch latency by providing a dynamically reconfigurable instruction pipeline for SIWs requiring a VLIW to be fetched. By introducing an additional cycle in the pipeline only when a VLIW fetch is required, the present invention solves the VLIW memory access problem. The pipeline stays in an expanded state, in general, until a branch type or load VLIW memory type operation is detected returning the pipeline to a compressed pipeline operation. By compressing the pipeline when a branch type operation is detected, the need for an additional cycle for the branch operation is avoided. Consequently, the shorter compressed pipeline provides more efficient performance for branch intensive control code as compared to a fixed pipeline with an expanded number of pipeline stages. In addition, the dynamic reconfigurable pipeline is scalable allowing each processing element (PE) in an array of PEs to expand and compress the pipeline in synchronism allowing iVLIW operations to execute independently in each PE. This is accomplished by having distributed pipelines in operation in parallel, one in each PE and in the controller sequence processor (SP).
摘要翻译： ManArray处理器管线设计通过为需要获取VLIW的SIW提供动态可重配置的指令流水线来解决间接VLIW存储器访问问题，而不会增加分支延迟。通过仅在需要VLIW提取时引入额外的循环，本发明解决了VLIW存储器访问问题。通常，管线保持在扩展状态，直到检测到分支类型或负载VLIW存储器类型操作，将流水线返回到压缩管道操作。当检测到分支类型操作时通过压缩流水线，避免了用于分支操作的附加周期的需要。因此，与具有扩展数量的流水线级的固定管道相比，较短的压缩流水线为分支密集型控制代码提供了更高效的性能。此外，动态可重配置流水线是可扩展的，允许PE阵列中的每个处理元件（PE）同步地扩展和压缩流水线，从而允许iVLIW操作在每个PE中独立执行。这是通过并行运行分布式管道，每个PE中的一个和控制器序列处理器（SP）中实现的。

15. 发明授权

US06557094B2 Methods and apparatus for scalable instruction set architecture with dynamic compact instructions 有权
公开(公告)号：US06557094B2
公开(公告)日：2003-04-29
申请号：US09969077
申请日：2001-09-28
申请人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
发明人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
IPC分类号： G06F1580
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30149 , G06F9/30178 , G06F9/30181 , G06F9/382 , G06F9/3885
摘要： A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs. In addition, the ManArray ISA is defined as a hierarchy of ISAs which allows for future growth in instruction capability and supports the packing of multiple instructions within a hierarchy of instructions.

16. 发明授权

US06467036B1 Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor 有权
标题翻译：用于动态超长指令字子指令选择的方法和装置，用于间接非常长的指令字处理器中的执行时间并行性
公开(公告)号：US06467036B1
公开(公告)日：2002-10-15
申请号：US09717992
申请日：2000-11-21
申请人： Gerald G. Pechanek , Juan Guillermo Revilla , Edwin F. Barry
发明人： Gerald G. Pechanek , Juan Guillermo Revilla , Edwin F. Barry
IPC分类号： G06F1580
CPC分类号： G06F9/3842 , G06F9/3017 , G06F9/3822 , G06F9/3853
摘要： A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory for storing very-long-instruction-words (VLIWs) used in operations involving the execution of two or more functional units in parallel. Each VLIW comprises a plurality of short-instruction-words (SIWs) where each SIW corresponds to a unique type of instruction associated with a unique functional unit. VLIWs are composed in the VLIW memory by loading and concatenating SIWs in each address, or entry. VLIWs are executed via the execute-VLIW (XV) instruction. The iVLIWs can be compressed at a VLIW memory address by use of a mask field contained within the XV1 instruction which specifies which functional units are enabled, or disabled, during the execution of the VLIW. The mask can be changed each time the XV1 instruction is executed, effectively modifying the VLIW every time it is executed. The VLIW memory (VIM) can be further partitioned into separate memories each associated with a function decode-and-execute unit. With a second execute VLIW instruction XV2, each functional unit's VIM can be independently addressed thereby removing duplicate SIWs within the functional unit's VIM. This provides a further optimization of the VLIW storage thereby allowing the use of smaller VLIW memories in cost sensitive applications.
摘要翻译：流水线数据处理单元包括指令定序器和能够并行执行n个操作的n个功能单元。指令定序器包括用于存储在涉及并行执行两个或多个功能单元的操作中使用的非常长的指令字（VLIW）的随机存取存储器。每个VLIW包括多个短指令字（SIW），其中每个SIW对应于与唯一功能单元相关联的唯一类型的指令。 VLIW通过在每个地址或条目中加载和连接SIW来组成VLIW存储器。 VLIW通过执行VLIW（XV）指令执行。通过使用XV1指令中包含的掩码字段，可以在VLIW存储器地址处压缩iVLIW，该掩码字段指定在执行VLIW期间启用或禁用哪些功能单元。每次执行XV1指令时，可以更改掩码，每次执行时都可以有效地修改VLIW。 VLIW存储器（VIM）可以被进一步划分成各自与功能解码和执行单元相关联的存储器。通过第二执行VLIW指令XV2，可以独立地对每个功能单元的VIM进行寻址，从而去除功能单元的VIM内的重复SIW。这提供了VLIW存储器的进一步优化，从而允许在成本敏感的应用中使用较小的VLIW存储器。

17. 发明授权

US06460120B1 Network processor, memory organization and methods 失效
标题翻译：网络处理器，内存组织和方法
公开(公告)号：US06460120B1
公开(公告)日：2002-10-01
申请号：US09384744
申请日：1999-08-27
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Piyush Chunilal Patel , Juan Guillermo Revilla , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Piyush Chunilal Patel , Juan Guillermo Revilla , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F1300
CPC分类号： H04Q11/0478 , H04L2012/5681
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.
摘要翻译：一种网络交换设备，用于这种设备的部件，以及操作这样的设备的方法，其中通过多个存储器元件和形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性。存储器元件和接口处理器一起形成一个网络处理器，能够在执行指导网络中的数据流的指令中与其它元件协作。存储元件的访问以特定方式和操作规则进行控制，这些规则由多个处理器提供对多个存储器元件的受控多次访问。

18. 发明授权

US06321322B1 Methods and apparatus for scalable instruction set architecture with dynamic compact instructions 有权
标题翻译：用于具有动态紧凑指令的可扩展指令集架构的方法和装置
公开(公告)号：US06321322B1
公开(公告)日：2001-11-20
申请号：US09543473
申请日：2000-04-05
申请人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
发明人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
IPC分类号： G06F1580
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30149 , G06F9/30178 , G06F9/30181 , G06F9/382 , G06F9/3885
摘要： A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs. In addition, the ManArray ISA is defined as a hierarchy of ISAs which allows for future growth in instruction capability and supports the packing of multiple instructions within a hierarchy of instructions.
摘要翻译：分层指令集架构（ISA）提供可插拔指令集功能和阵列处理器的支持。术语pluggable来自程序员的观点，并且涉及可以容易地添加到处理器架构中以用于代码密度和性能增强的指令组。本文所述的一个具体方面是独特的压缩指令集，其允许程序员能够通过任务为任务动态地创建一组压缩指令，以提高控制和并行代码密度的主要目的。这些压缩指令是可并行的，因为它们不特别地限于控制代码应用，而是可以在阵列处理器中的处理元件（PE）中执行。 ManArray系列处理器专为此动态压缩指令集功能而设计，并且还支持从一个到N个PE的可扩展阵列。此外，ManArray ISA被定义为ISA的层次结构，其允许未来指令能力的增长并且支持在指令层次结构内的多个指令的打包。

19. 发明授权

US06173389B2 Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor 有权
标题翻译：用于动态超长指令字子指令选择的方法和装置，用于间接非常长的指令字处理器中的执行时间并行性
公开(公告)号：US06173389B2
公开(公告)日：2001-01-09
申请号：US09205588
申请日：1998-12-04
申请人： Gerald G. Pechanek , Juan Guillermo Revilla , Edwin F. Barry
发明人： Gerald G. Pechanek , Juan Guillermo Revilla , Edwin F. Barry
IPC分类号： G06F1580
CPC分类号： G06F9/3842 , G06F9/3017 , G06F9/3822 , G06F9/3853
摘要： A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory for storing very-long-instruction-words (VLIWs) used in operations involving the execution of two or more functional units in parallel. Each VLIW comprises a plurality of short-instruction-words (SIWs) where each SIW corresponds to a unique type of instruction associated with a unique functional unit. VLIWs are composed in the VLIW memory by loading and concatenating SIWs in each address, or entry. VLIWs are executed via the execute-VLIW (XV) instruction. The iVLIWs can be compressed at a VLIW memory address by use of a mask field contained within the XV1 instruction which specifics which functional units are enabled, or disabled, during the execution of the VLIW. The mask can be changed each time the XV1 instruction is executed, effectively modifying the VLIW every time it is executed. The VLIW memory (VIM) can be further partitioned into separate memories each associated with a function decode-and-execute unit. With a second execute VLIW instruction XV2, each functional unit's VIM can be independently addressed thereby removing duplicate SIWs within the functional unit's VIM. This provides a further optimization of the VLIW storage thereby allowing the use of smaller VLIW memories in cost sensitive applications.
摘要翻译：流水线数据处理单元包括指令定序器和能够并行执行n个操作的n个功能单元。指令定序器包括用于存储在涉及并行执行两个或多个功能单元的操作中使用的非常长指令字（VLIW）的随机存取存储器。每个VLIW包括多个短指令字（SIW），其中每个SIW对应于与唯一功能单元相关联的唯一类型的指令。 VLIW通过在每个地址或条目中加载和连接SIW来组成VLIW存储器。 VLIW通过执行VLIW（XV）指令执行。通过使用包含在XV1指令中的掩码字段，可以在VLIW存储器地址处压缩iVLIW，该掩码字段指定在执行VLIW期间启用或禁用哪些功能单元。每次执行XV1指令时，可以更改掩码，每次执行时都可以有效地修改VLIW。 VLIW存储器（VIM）可以被进一步划分成各自与功能解码和执行单元相关联的存储器。通过第二执行VLIW指令XV2，可以独立地对每个功能单元的VIM进行寻址，从而去除功能单元的VIM内的重复SIW。这提供了VLIW存储器的进一步优化，从而允许在成本敏感的应用中使用较小的VLIW存储器。

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