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    • 11. 再颁专利
    • CDMA receiver with parallel interference suppression and optimized synchronization
    • CDMA接收机具有并行干扰抑制和优化同步
    • USRE40716E1
    • 2009-06-02
    • US11593123
    • 2006-11-02
    • Laurent OuvryDidier VarreauDidier LattardSebastien Leveque
    • Laurent OuvryDidier VarreauDidier LattardSebastien Leveque
    • H04B1/00
    • H04B1/71075H04B1/7093H04B1/7095
    • A receiver for transmission and parallel interference has multiple access interference suppression stages having K channels, each comprising a correlation device corresponding to a particular pseudorandom sequence and interference generation and suppression device. Each stage delivers to the following stage signals at least partly freed from multiple access interferences. A decision stage receives the signals from the channels of the preceding suppression stage. Each decision stage has a correlation device corresponding to one of the pseudorandom sequences and decision device to deliver data. Devices for producing synchronization signals can control the interference suppression and the decision device. The devices producing the synchronization signals have components placed in the channels of the final stage. Further, the synchronization signals produced by these devices control the decision device of the channels of the final stage and the interference estimation device of the at least one interference suppression stages following appropriate time shifts.
    • 用于传输和并行干扰的接收机具有具有K个信道的多个接入干扰抑制级,每个信道包括对应于特定伪随机序列和干扰产生和抑制装置的相关装置。 每个阶段至少部分地从多个接入干扰中释放出下一个阶段的信号。 判定级从前述抑制级的通道接收信号。 每个决策阶段具有对应于伪随机序列和决策装置之一的相关装置以递送数据。 用于产生同步信号的装置可以控制干扰抑制和决策装置。 产生同步信号的装置具有放置在最后级的通道中的部件。 此外,由这些装置产生的同步信号在适当的时移之后控制最后级的信道的判定装置和至少一个干扰抑制阶段的干扰估计装置。
    • 12. 发明授权
    • CDMA receiver with parallel interference suppression and optimized synchronization
    • CDMA接收机具有并行干扰抑制和优化同步
    • US06813308B1
    • 2004-11-02
    • US09598372
    • 2000-06-21
    • Laurent OuvryDidier VarreauDidier LattardSébastien Leveque
    • Laurent OuvryDidier VarreauDidier LattardSébastien Leveque
    • H04B1707
    • H04B1/71075H04B1/7093H04B1/7095
    • A receiver for transmission and parallel interference has multiple access interference suppression stages having K channels, each comprising a correlation device corresponding to a particular pseudorandom sequence and interference generation and suppression device. Each stage delivers to the following stage signals at least partly freed from multiple access interferences. A decision stage receives the signals from the channels of the preceding suppression stage. Each decision stage has a correlation device corresponding to one of the pseudorandom sequences and decision device to deliver data. Devices for producing synchronization signals can control the interference suppression and the decision device. The devices producing the synchronization signals have components placed in the channels of the final stage. Further ,the synchronization signals produced by these devices control the decision device of the channels of the final stage and the interference estimation device of the at least one interference suppression stages following appropriate time shifts.
    • 用于传输和并行干扰的接收机具有具有K个信道的多个接入干扰抑制级,每个信道包括对应于特定伪随机序列和干扰产生和抑制装置的相关装置。 每个阶段至少部分地从多个接入干扰中释放出下一个阶段的信号。 判定级从前述抑制级的通道接收信号。 每个决策阶段具有对应于伪随机序列和决策装置之一的相关装置以递送数据。 用于产生同步信号的装置可以控制干扰抑制和决策装置。 产生同步信号的装置具有放置在最后级的通道中的部件。 此外,由这些装置产生的同步信号在适当的时移之后控制最后级的信道的判定装置和至少一个干扰抑制阶段的干扰估计装置。