专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US5885847A Method of fabricating a compound semiconductor device 失效
标题翻译：制造化合物半导体器件的方法
公开(公告)号：US5885847A
公开(公告)日：1999-03-23
申请号：US835957
申请日：1997-04-11
申请人： Hyung-Sup Yoon , Jin-Hee Lee , Byung-Sun Park , Chul-Sun Park , Kwang-Eui Pyun
发明人： Hyung-Sup Yoon , Jin-Hee Lee , Byung-Sun Park , Chul-Sun Park , Kwang-Eui Pyun
IPC分类号： H01L29/778 , H01L21/20 , H01L21/205 , H01L27/144 , H01L21/00 , H01L21/338
CPC分类号： H01L27/1443
摘要： The invention relates to a method of fabricating a compound semiconductor device by forming a first and a second compound semiconductor devices having a plurality of different epitaxial layers on a common semiconductor substrate. The method comprises the steps of sequentially forming a plurality of first epitaxial layers for manufacturing the first compound semiconductor device on the semiconductor substrate; forming a first insulating film pattern for defining an active region of the first compound semiconductor device; etching the plurality of first epitaxial layers using the first insulating film pattern as a mask; forming a second insulating film on the resultant structure; forming a sidewall insulating spacer on the sidewall of the active region of the first compound semiconductor device by dry etching the second insulating film; sequentially forming a plurality of second epitaxial layers for manufacturing the second compound semiconductor device on the portion from which the plurality of first epitaxial layers is etched back; forming each electrode of the first and second compound semiconductor devices; and forming an interconnection electrode interconnecting each electrode of the first and second compound semiconductor devices.
摘要翻译：本发明涉及通过在公共半导体衬底上形成具有多个不同外延层的第一和第二化合物半导体器件来制造化合物半导体器件的方法。该方法包括以下步骤：在半导体衬底上依次形成用于制造第一化合物半导体器件的多个第一外延层; 形成用于限定所述第一化合物半导体器件的有源区的第一绝缘膜图案; 使用第一绝缘膜图案作为掩模蚀刻多个第一外延层; 在所得结构上形成第二绝缘膜; 通过干蚀刻所述第二绝缘膜，在所述第一化合物半导体器件的有源区的侧壁上形成侧壁绝缘间隔物; 在多个第一外延层被回蚀的部分上依次形成用于制造第二化合物半导体器件的多个第二外延层; 形成第一和第二化合物半导体器件的每个电极; 以及形成互连所述第一和第二化合物半导体器件的每个电极的互连电极。

12. 发明授权

US5856232A Method for fabricating T-shaped electrode and metal layer having low resistance 失效
标题翻译：用于制造具有低电阻的T形电极和金属层的方法
公开(公告)号：US5856232A
公开(公告)日：1999-01-05
申请号：US675972
申请日：1996-07-05
申请人： Jeon-Wook Yang , Eung-Gee Oh , Byung-Sun Park , Chul-Sun Park , Kwang-Eui Pyun
发明人： Jeon-Wook Yang , Eung-Gee Oh , Byung-Sun Park , Chul-Sun Park , Kwang-Eui Pyun
IPC分类号： H01L21/28 , H01L21/285 , H01L21/338 , H01L29/41 , H01L29/812
CPC分类号： H01L21/28587 , H01L21/28581 , Y10S148/10
摘要： A method for fabricating a T-shaped gate electrode includes the steps of: forming a fine gate pattern on a semiconductor substrate; forming an insulating layer on the semiconductor substrate on which the gate pattern is formed, and forming a planarizing layer on the insulating layer to planarize the surface of the semiconductor substrate; etching the planarizing layer to expose the top of the insulating layer; isotropically etching the insulating layer to expose the gate pattern using the planarizing layer as a mask; etching the exposed gate pattern to selectively expose the semiconductor substrate; depositing a gate metal to cover the exposed substrate, the insulating layer and the planarizing layer, to form a T-shaped gate; and simultaneously removing the planarizing layer, thereby forming a T-shaped gate metal with improved productivity.
摘要翻译：一种制造T形栅电极的方法包括以下步骤：在半导体衬底上形成精细栅极图案; 在其上形成有栅极图案的半导体衬底上形成绝缘层，并在绝缘层上形成平坦化层以使半导体衬底的表面平坦化; 蚀刻平坦化层以暴露绝缘层的顶部; 使用平坦化层作为掩模，各向同性蚀刻绝缘层以露出栅极图案; 蚀刻暴露的栅极图案以选择性地暴露半导体衬底; 沉积栅极金属以覆盖暴露的基板，绝缘层和平坦化层，以形成T形门; 同时除去平坦化层，从而形成T形门金属，生产率提高。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式