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11. 发明授权

US09227378B2 Methods, devices and processes for multi-state phase change devices 有权
公开(公告)号：US09227378B2
公开(公告)日：2016-01-05
申请号：US13568509
申请日：2012-08-07
申请人： Davide Colombo , Davide Erbetta
发明人： Davide Colombo , Davide Erbetta
IPC分类号： G11C11/00 , B32B7/02 , B44C1/22 , G11C11/56 , G11C13/00
CPC分类号： G11C11/5678 , B32B7/02 , B44C1/22 , G11C13/0004 , G11C13/0069 , G11C13/0097 , G11C2013/0078 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1666 , Y10T428/24942
摘要： Devices include multiple phase change materials connected in parallel between electrodes. Memory cells with multiple parallel phase change materials can be programmed to transition among more than two states representing multiple bits of information. Methods for manufacture and use are also disclosed.

12. 发明申请

US20080217776A1 Process for manufacturing integrated circuits formed on a semiconductor substrate and comprising tungsten layers 审中-公开
标题翻译：用于制造形成在半导体衬底上并且包括钨层的集成电路的工艺
公开(公告)号：US20080217776A1
公开(公告)日：2008-09-11
申请号：US12074776
申请日：2008-03-05
申请人： Maria Santina Marangon , Davide Erbetta
发明人： Maria Santina Marangon , Davide Erbetta
IPC分类号： H01L21/768 , H01L23/538
CPC分类号： H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L21/76877
摘要： An embodiment is described for manufacturing integrated circuits formed on a semiconductor substrate, which embodiment comprises forming a cobalt suicide layer on said semiconductor substrate, forming a layer comprising tungsten on said silicide layer, said cobalt suicide layer forming a barrier against the migration of the silicon atoms of said semiconductor substrate during the formation step of said layer comprising tungsten. An embodiment is also described for manufacturing contacts comprising tungsten of an integrated circuit formed on a semiconductor substrate.
摘要翻译：描述了用于制造形成在半导体衬底上的集成电路的实施例，该实施例包括在所述半导体衬底上形成硅化硅层，在所述硅化物层上形成包含钨的层，所述硅化钴层形成阻挡硅迁移的阻挡层在包含钨的所述层的形成步骤期间所述半导体衬底的原子。还描述了用于制造包括形成在半导体衬底上的集成电路的钨的触点的实施例。

13. 发明授权

US08680499B2 Memory cells 有权
标题翻译：记忆单元
公开(公告)号：US08680499B2
公开(公告)日：2014-03-25
申请号：US13355904
申请日：2012-01-23
申请人： Davide Erbetta , Luca Fumagalli , Innocenzo Tortorelli , Enrico Varesi
发明人： Davide Erbetta , Luca Fumagalli , Innocenzo Tortorelli , Enrico Varesi
IPC分类号： H01L29/02
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148
摘要： Some embodiments include memory cells which contain chalcogenide material having germanium in combination with one or both of antimony and tellurium. An atomic percentage of the germanium within the chalcogenide material is greater than 50%; and may be, for example, within a range of from greater than or equal to about 52% to less than or equal to about 78%. In some embodiments, the memory cell has a top electrode over the chalcogenide material, a heater element under and directly against the chalcogenide material, and a bottom electrode beneath the heater element. The heater element may be L-shaped, with the L-shape having a vertical pillar region joining with a horizontal leg region. A bottom surface of the horizontal leg region may be directly against the bottom electrode, and a top surface of the vertical pillar region may be directly against the chalcogenide material.
摘要翻译：一些实施方案包括含有具有与锑和碲中的一种或两者结合的锗的硫族化物材料的记忆体。硫族化物材料中锗的原子百分比大于50％; 并且可以例如在大于或等于约52％至小于或等于约78％的范围内。在一些实施例中，存储器单元具有位于硫属化物材料上的顶部电极，位于硫酸化物材料之下并直接抵靠硫族化物材料的加热器元件，以及加热元件下方的底部电极。加热元件可以是L形，L形具有与水平支腿区域连接的垂直柱状区域。水平支腿区域的底面可以直接抵靠底部电极，并且垂直柱状区域的顶表面可以直接抵靠硫族化物材料。

14. 发明授权

US08227785B2 Chalcogenide containing semiconductors with chalcogenide gradient 有权
标题翻译：含硫族化合物的半导体与硫属化物梯度
公开(公告)号：US08227785B2
公开(公告)日：2012-07-24
申请号：US12944119
申请日：2010-11-11
申请人： Davide Erbetta
发明人： Davide Erbetta
IPC分类号： H01L47/00 , H01L29/04 , H01L29/06 , H01L21/00 , H01L21/06
CPC分类号： H01L45/06 , H01L45/00 , H01L45/141 , H01L45/144 , H01L45/1641
摘要： Chalcogenide containing semiconductor devices may be formed with a gradient film between a chalcogenide film and another film. The gradient film may have its chalcogenide concentration decrease as it extends away from the chalcogenide film, while the concentration of the other film material increases across the thickness of the gradient film moving away from the chalcogenide film.
摘要翻译：含硫族化物的半导体器件可以由硫族化物膜和另一膜之间的梯度膜形成。梯度膜的硫属元素浓度随着其远离硫族化物膜而降低，而另一种薄膜材料的浓度则跨越离开硫族化物膜的梯度薄膜的厚度增加。

15. 发明申请

US20120119177A1 Chalcogenide Containing Semiconductors with Chalcogenide Gradient 有权
标题翻译：含硫族化合物梯度的含硫属化合物
公开(公告)号：US20120119177A1
公开(公告)日：2012-05-17
申请号：US12944119
申请日：2010-11-11
申请人： Davide Erbetta
发明人： Davide Erbetta
IPC分类号： H01L45/00 , H01L21/62
CPC分类号： H01L45/06 , H01L45/00 , H01L45/141 , H01L45/144 , H01L45/1641
摘要： Chalcogenide containing semiconductor devices may be formed with a gradient film between a chalcogenide film and another film. The gradient film may have its chalcogenide concentration decrease as it extends away from the chalcogenide film, while the concentration of the other film material increases across the thickness of the gradient film moving away from the chalcogenide film.
摘要翻译：含硫族化物的半导体器件可以由硫族化物膜和另一膜之间的梯度膜形成。梯度膜的硫属元素浓度随着其远离硫族化物膜而降低，而另一种薄膜材料的浓度则跨越离开硫族化物膜的梯度薄膜的厚度增加。

16. 发明申请

US20060180850A1 Process for manufacturing a memory with local electrical contact between the source line and the well 审中-公开
标题翻译：用于制造在源极线和阱之间具有局部电接触的存储器的工艺
公开(公告)号：US20060180850A1
公开(公告)日：2006-08-17
申请号：US11331826
申请日：2006-01-12
申请人： Daniela Brazzelli , Giorgio Servalli , Davide Erbetta , Maria Marangon
发明人： Daniela Brazzelli , Giorgio Servalli , Davide Erbetta , Maria Marangon
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A process for manufacturing a memory having a plurality of memory cells includes the steps of forming a well (having a first type of conductivity) within a wafer of semiconductor material, defining active regions within the well extending in a first direction, forming memory cells within the active regions (each memory cell having a source region with a second type of conductivity opposite to the first type of conductivity), and forming lines of electrical contact which electrically contact source regions aligned in a second direction. The step of forming lines of electrical contact includes forming an electrical contact between the source regions and portions of the well adjacent thereto in the second direction. The memory accordingly includes lines of electrical contact, each in electrical contact with source regions aligned along a respective row, wherein the lines of electrical contact further provide an electrical contact between the source regions and portions of the well adjacent thereto along said rows.
摘要翻译：一种用于制造具有多个存储单元的存储器的方法包括以下步骤：在半导体材料的晶片内形成阱（具有第一类型的导电性），限定在第一方向上延伸的阱内的有源区，形成存储单元内有源区（每个存储单元具有与第一类型的导电性相反的第二类型的导电性的源极区），以及形成与第二方向对准的电接触的电接触线。形成电接触线的步骤包括在第二方向上在源极区域和与其相邻的阱的部分之间形成电接触。存储器相应地包括电接触线，每条电路与沿着相应行排列的源区电接触，其中电接触线还提供沿着所述行的源极区域和与其相邻的阱的部分之间的电接触。

17. 发明申请

US20140034892A1 PHASE CHANGE MATERIAL GRADIENT STRUCTURES AND METHODS 有权
标题翻译：相变材料梯度结构和方法
公开(公告)号：US20140034892A1
公开(公告)日：2014-02-06
申请号：US13566375
申请日：2012-08-03
申请人： Davide Erbetta , Luca Fumagalli
发明人： Davide Erbetta , Luca Fumagalli
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L45/06 , H01L27/2427 , H01L45/144 , H01L45/1616 , H01L45/1625 , H01L45/165 , H01L45/1675
摘要： Memory cells and memory cell structures having a number of phase change material gradients, devices utilizing the same, and methods of forming the same are disclosed herein. One example of forming a memory cell includes forming a first electrode material, forming a phase change material gradient on the first electrode material, and forming a second electrode material on the phase change material gradient.
摘要翻译：本文公开了具有多个相变材料梯度的存储单元和存储单元结构，利用其的器件及其形成方法。形成存储单元的一个实例包括形成第一电极材料，在第一电极材料上形成相变材料梯度，以及在相变材料梯度上形成第二电极材料。

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