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    • 12. 发明申请
    • DUAL-METAL SELF-ALIGNED WIRES AND VIAS
    • 双金属自对准线和VIAS
    • US20130207270A1
    • 2013-08-15
    • US13371493
    • 2012-02-13
    • Steven J. HolmesDavid V. HorakCharles W. Koburger, IIIShom PonothChih-Chao Yang
    • Steven J. HolmesDavid V. HorakCharles W. Koburger, IIIShom PonothChih-Chao Yang
    • H01L21/768H01L23/49
    • H01L23/485H01L21/76885H01L21/76897H01L23/5283H01L23/53266H01L2924/0002H01L2924/00
    • Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features.
    • 形成半导体结构的方法,包括在半导体衬底上形成第一导电间隔物; 相对于所述第一导电间隔物形成第二导电间隔物,所述第二导电间隔物中的至少一个与所述第一导电间隔物中的每一个相邻并与之接触以形成组合的导电间隔物; 相对于第一导电间隔物使第二导电间隔物凹陷,使得第一导电间隔物延伸超过第二导电间隔物; 沉积ILD以覆盖除了第一导电间隔物的暴露边缘之外的第一和第二间隔物; 图案化第一导电间隔物的暴露边缘以将预定位置中的第一导电间隔物的边缘凹入以形成相对于ILD的凹部; 并用绝缘材料填充凹槽,以将第一导电间隔物的未加工的边缘作为过孔留下以后的布线特征。
    • 13. 发明申请
    • Hybrid Copper Interconnect Structure and Method of Fabricating Same
    • 混合铜互连结构及其制造方法
    • US20130026635A1
    • 2013-01-31
    • US13191999
    • 2011-07-27
    • Chih-Chao YangDavid V. HorakCharles W. Koburger, IIIShom Ponoth
    • Chih-Chao YangDavid V. HorakCharles W. Koburger, IIIShom Ponoth
    • H01L23/52H01L21/768
    • H01L23/53238H01L21/76841H01L21/76843H01L21/76847H01L21/76877H01L21/76882H01L2924/0002H01L2924/00
    • A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region. The copper regions containing the different impurities levels can be achieved utilizing a combination of physical vapor deposition of a copper region having a low impurity level (i.e., less than 20 ppm) and copper reflow, with electroplating another copper region having a high impurity level (i.e., 100 ppm or greater).
    • 提供了包含在相同开口内具有不同杂质水平的铜区域的混合互连结构。 在一个实施例中,互连结构包括具有位于其中的至少一个开口的图案化电介质材料。 双材料衬垫至少位于所述至少一个开口内的图案化电介质材料的侧壁上。 所述结构还包括具有位于所述至少一个开口的底部区域内的第一杂质水平的第一铜区域和具有位于所述至少一个开口的顶部区域内的第二杂质水平的第二铜区域和位于所述第一铜 地区。 根据本公开,第一铜区域的第一杂质水平不同于第二铜区域的第二杂质水平。 可以利用具有低杂质水平(即小于20ppm)的铜区域和铜回流的物理气相沉积与电镀另一个具有高杂质水平的铜区域的组合来实现含有不同杂质水平的铜区域 即100ppm以上)。