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11. 发明授权

US06951825B2 Method of etching a SiN/Ir/TaN or SiN/Ir/Ti stack using an aluminum hard mask 失效
标题翻译：使用铝硬掩模蚀刻SiN / Ir / TaN或SiN / Ir / Ti叠层的方法
公开(公告)号：US06951825B2
公开(公告)日：2005-10-04
申请号：US10391294
申请日：2003-03-17
申请人： Tingkai Li , Bruce D. Ulrich , David R. Evans , Sheng Teng Hsu
发明人： Tingkai Li , Bruce D. Ulrich , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/3065 , H01L21/02 , H01L21/311 , H01L21/3213 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792 , H01L21/302
CPC分类号： H01L21/32136 , H01L21/31116 , H01L21/32139 , H01L28/65
摘要： A method of etching includes preparing a substrate; depositing a first etch stop layer; forming an iridium bottom electrode layer; depositing a SiN layer; depositing and patterning an aluminum hard mask; etching a non-patterned SiN layer with a SiN selective etchant, stopping at the level of the iridium bottom electrode layer; etching the first etch stop layer with a second selective etchant; depositing an oxide layer and CMP the oxide layer to the level of the remaining SiN layer; wet etching the SiN layer to form a trench; depositing a layer of ferroelectric material in the trench formed by removal of the SiN layer; depositing a layer of high-k oxide; and completing the device, including metallization.
摘要翻译：蚀刻方法包括准备基板; 沉积第一蚀刻停止层; 形成铱底电极层; 沉积SiN层; 沉积和图案化铝硬掩模; 用SiN选择性蚀刻剂蚀刻未图案化的SiN层，停止在铱底部电极层的水平面上; 用第二选择性蚀刻剂蚀刻第一蚀刻停止层; 将氧化物层沉积并将所述氧化物层CMP沉积到剩余SiN层的水平; 湿式蚀刻SiN层以形成沟槽; 在通过去除SiN层形成的沟槽中沉积一层铁电材料; 沉积一层高K氧化物; 并完成设备，包括金属化。

12. 发明授权

US07364665B2 Selective etching processes of SiO2 , Ti and In2 O3 thin films for FeRAM device applications 失效
标题翻译：用于FeRAM器件应用的SiO2，Ti和In2 O3薄膜的选择性蚀刻工艺
公开(公告)号：US07364665B2
公开(公告)日：2008-04-29
申请号：US10970885
申请日：2004-10-21
申请人： Tingkai Li , Bruce D. Ulrich , David R. Evans , Sheng Teng Hsu
发明人： Tingkai Li , Bruce D. Ulrich , David R. Evans , Sheng Teng Hsu
IPC分类号： B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L29/6684 , C23F4/00 , H01L21/28291 , H01L21/31116 , H01L21/32136
摘要： A method of selectively etching a three-layer structure consisting of SiO2, In2O3, and titanium, includes etching the SiO2, stopping at the titanium layer, using C3F8 in a range of between about 10 sccm to 30 sccm; argon in a range of between about 20 sccm to 40 sccm, using an RF source in a range of between about 1000 watts to 3000 watts and an RF bias in a range of between about 400 watts to 800 watts at a pressure in a range of between about 2 mtorr to 6 mtorr; and etching the titanium, stopping at the In2O3 layer, using BCl in a range of between about 10 sccm to 50 sccm; chlorine in a range of between about 40 sccm to 80 sccm, a Tcp in a range of between about 200 watts to 500 watts at an RF bias in a range of between about 100 watts to 200 watts at a pressure in a range of between about 4 mtorr to 8 mtorr.
摘要翻译：选择性地蚀刻由SiO 2，In 2 O 3 N 3和Ti构成的三层结构的方法包括蚀刻SiO _{2 ，在钛层上停止，使用C 3 3 F 8 N在约10sccm至30sccm之间; 在约20sccm至40sccm的范围内的氩气，使用在约1000瓦特至3000瓦特之间的范围内的RF源和在约400瓦特至800瓦特范围内的RF偏压，约2mtorr至6mtorr; 并且使用在约10sccm至50sccm之间的范围内的BCl蚀刻钛，停止在In 2 N 3 O 3层处; 在约40sccm至80sccm的范围内的氯，在约200瓦特至200瓦特之间的RF偏压下在约200瓦特至500瓦特之间的范围内的T cp < 在约4mtorr至8mtorr的范围内的压力。}

13. 发明授权

US06794198B1 MOCVD selective deposition of c-axis oriented Pb5Ge3O11 thin films on high-k gate oxides 失效
标题翻译：在高k栅极氧化物上的c轴取向Pb5Ge3O11薄膜的MOCVD选择性沉积
公开(公告)号：US06794198B1
公开(公告)日：2004-09-21
申请号：US10606057
申请日：2003-06-25
申请人： Tingkai Li , Sheng Teng Hsu , David R. Evans , Bruce D. Ulrich
发明人： Tingkai Li , Sheng Teng Hsu , David R. Evans , Bruce D. Ulrich
IPC分类号： H01L2100
CPC分类号： H01L21/31691 , C23C16/0209 , C23C16/40 , C23C16/56 , H01L21/31604
摘要： A method of forming a PGO thin film on a high-k dielectric includes preparing a silicon substrate, including forming a high-k gate oxide layer thereon; patterning the high-k gate oxide; annealing the substrate in a first annealing step; placing the substrate in a MOCVD chamber; depositing a PGO thin film by injecting a PGO precursor into the MOCVD chamber; and annealing the structure having a PGO thin film on a high-k gate oxide in a second annealing step.
摘要翻译：在高k电介质上形成PGO薄膜的方法包括制备硅衬底，包括在其上形成高k栅极氧化物层; 图案化高k栅极氧化物; 在第一退火步骤中退火衬底; 将基板放置在MOCVD室中; 通过将PGO前体注入到MOCVD室中来沉积PGO薄膜; 以及在第二退火步骤中在高k栅极氧化物上退火具有PGO薄膜的结构。

14. 发明授权

US07098043B2 PCMO spin-coat deposition 有权
标题翻译： PCMO旋涂沉积
公开(公告)号：US07098043B2
公开(公告)日：2006-08-29
申请号：US10759468
申请日：2004-01-15
申请人： Wei-Wei Zhuang , Lisa H. Stecker , Gregory M. Stecker , Sheng Teng Hsu
发明人： Wei-Wei Zhuang , Lisa H. Stecker , Gregory M. Stecker , Sheng Teng Hsu
IPC分类号： H01L21/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608 , H01L45/1683
摘要： A Pr1-XCaXMnO3 (PCMO) spin-coat deposition method for eliminating voids is provided, along with a void-free PCMO film structure. The method comprises: forming a substrate, including a noble metal, with a surface; forming a feature, such as a via or trench, normal with respect to the substrate surface; spin-coating the substrate with acetic acid; spin-coating the substrate with a first, low concentration of PCMO solution; spin-coating the substrate with a second concentration of PCMO solution, having a greater concentration of PCMO than the first concentration; baking and RTA annealing (repeated one to five times); post-annealing; and, forming a PCMO film with a void-free interface between the PCMO film and the underlying substrate surface. The first concentration of PCMO solution has a PCMO concentration in the range of 0.01 to 0.1 moles (M). The second concentration of PCMO solution has a PCMO concentration in the range of 0.2 to 0.5 M.
摘要翻译：提供了一种用于消除空隙的Pr 1-X C 3 Mn 3 O 3（PCMO）旋涂沉积方法，以及无空隙 PCMO薄膜结构。该方法包括：用表面形成包括贵金属的基底; 形成相对于衬底表面正常的特征，例如通孔或沟槽; 用乙酸旋涂底物; 用第一种低浓度的PCMO溶液旋涂底物; 以第二浓度的PCMO溶液旋涂底物，其具有比第一浓度更高浓度的PCMO; 烘烤和RTA退火（重复1〜5次）; 后退火; 并且在PCMO膜和下面的衬底表面之间形成具有无空隙界面的PCMO膜。 PCMO溶液的第一浓度的PCMO浓度范围为0.01至0.1摩尔（M）。 PCMO溶液的第二浓度的PCMO浓度范围为0.2-0.5M。

15. 发明授权

US07462499B2 Carbon nanotube with ZnO asperities 失效
标题翻译：具有ZnO粗糙度的碳纳米管
公开(公告)号：US07462499B2
公开(公告)日：2008-12-09
申请号：US11262439
申请日：2005-10-28
申请人： John F. Conley, Jr. , Yoshi Ono , Lisa H. Stecker , Sheng Teng Hsu , Josh M. Green , Lifeng Dong , Jun Jiao
发明人： John F. Conley, Jr. , Yoshi Ono , Lisa H. Stecker , Sheng Teng Hsu , Josh M. Green , Lifeng Dong , Jun Jiao
IPC分类号： H01L21/00
CPC分类号： H01J9/025 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/162 , C01B32/168 , C01B2202/34 , C01B2202/36 , H01J1/304 , H01J2201/30469 , H01L21/0237 , H01L21/02381 , H01L21/02444 , H01L21/02472 , H01L21/02483 , H01L21/02513 , H01L21/02554 , H01L21/02601 , Y10S977/754
摘要： A ZnO asperity-covered carbon nanotube (CNT) device has been provided, along with a corresponding fabrication method. The method comprises: forming a substrate; growing CNTs from the substrate; conformally coating the CNTs with ZnO; annealing the ZnO-coated CNTs; and, forming ZnO asperities on the surface of the CNTs in response to the annealing. In one aspect, the ZnO asperities have a density in the range of about 100 to 1000 ZnO asperities per CNT. The density is dependent upon the deposited ZnO film thickness and annealing parameters. The CNTs are conformally coating with ZnO using a sputtering, chemical vapor deposition (CVD), spin-on, or atomic layer deposition (ALD). For example, an ALD process can be to deposit a layer of ZnO over the CNTs having a thickness in the range of 1.2 to 200 nanometers (nm).
摘要翻译：已经提供了ZnO微粒覆盖碳纳米管（CNT）器件，以及相应的制造方法。该方法包括：形成衬底; 从底物生长CNT; 用ZnO共形涂覆CNT; 退火ZnO涂层的CNT; 并且响应于退火在CNT的表面上形成ZnO粗糙度。在一个方面，ZnO粗糙度的密度在每个CNT约100-1000nm的ZnO粗糙度的范围内。密度取决于沉积的ZnO膜厚度和退火参数。使用溅射，化学气相沉积（CVD），旋涂或原子层沉积（ALD），使用ZnO共形涂覆CNT。例如，ALD工艺可以在厚度在1.2至200纳米（nm）范围内的CNT上沉积ZnO层。

16. 发明授权

US07675056B2 Germanium phototransistor with floating body 有权
标题翻译：具有浮体的锗光电晶体管
公开(公告)号：US07675056B2
公开(公告)日：2010-03-09
申请号：US11891574
申请日：2007-08-10
申请人： Jong-Jan Lee , Sheng Teng Hsu , Jer-Shen Maa , Douglas J. Tweet
发明人： Jong-Jan Lee , Sheng Teng Hsu , Jer-Shen Maa , Douglas J. Tweet
IPC分类号： H01L29/06 , H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/062 , H01L31/113 , H01L31/0232
CPC分类号： H01L31/1136 , H01L31/028 , H01L31/1808 , Y02E10/547
摘要： A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.
摘要翻译：提出了一种浮体锗（Ge）光电晶体管及其制造工艺。该方法包括：提供硅（Si）衬底; 选择性地形成覆盖Si衬底的绝缘体层; 使用液相外延（LPE）工艺形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成覆盖所述沟道区的栅极电介质，栅电极和栅极间隔; 并且在Ge层中形成源/漏区。 LPE工艺包括用具有大于第一温度的熔化温度的材料包封Ge，并且使用低于第一温度的温度来熔化Ge。 LPE工艺包括：形成覆盖沉积Ge的介电层; 融化Ge; 并且响应于冷却Ge，将外延生长前沿从下面的Si衬底表面横向传播到Ge中。

17. 发明授权

US07608874B2 Fully isolated photodiode stack 失效
标题翻译：全隔离光电二极管堆叠
公开(公告)号：US07608874B2
公开(公告)日：2009-10-27
申请号：US11657152
申请日：2007-01-24
申请人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H01L27/14647 , H01L27/1463 , H01L27/14689
摘要： An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, together with an associated fabrication method. The method provides a bulk silicon (Si) substrate. A plurality of color imager cells are formed, either in the Si substrate, or in a single epitaxial Si layer formed over the substrate. Each color imager cell includes a photodiode set with a first, second, and third photodiode formed as a stacked multi-junction structure. A U-shaped (in cross-section) well liner, fully isolates the photodiode set from adjacent photodiode sets in the array. For example, each photodiode is formed from a p doped Si layer physically interfaced to a first wall. A well bottom physically interfaces to the first wall, and the p doped Si layer of the third, bottom-most, photodiode is part of the well bottom. Then, the photodiode sets may be formed from an n/p/n/p/n/p or n/p/p−/p/p−/p layered structure.
摘要翻译：提供了完全隔离的多结互补金属氧化物半导体（CMOS）无滤膜彩色成像器单元的阵列，以及相关的制造方法。该方法提供体硅（Si）衬底。在Si衬底中或在衬底上形成的单个外延Si层中形成多个彩色成像器单元。每个彩色成像器单元包括具有形成为堆叠多结结构的第一，第二和第三光电二极管。 U形（横截面）井衬管，将阵列中的光电二极管组与相邻的光电二极管组完全隔离。例如，每个光电二极管由物理上与第一壁物理连接的p掺杂Si层形成。阱底部与第一壁物理接口，第三，最底部的光电二极管的p掺杂Si层是阱底部的一部分。然后，光电二极管组可以由n / p / n / p / n / p或n / p / p / p / p / p层叠结构形成。

18. 发明申请

US20080280426A1 Gallium nitride-on-silicon interface 审中-公开
标题翻译：氮化镓在硅界面
公开(公告)号：US20080280426A1
公开(公告)日：2008-11-13
申请号：US11801210
申请日：2007-05-09
申请人： Tingkai Li , Douglas J. Tweet , Jer-Shen Maa , Sheng Teng Hsu
发明人： Tingkai Li , Douglas J. Tweet , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L29/739 , H01L21/20
CPC分类号： C30B29/406 , C30B25/183 , H01L21/02381 , H01L21/02458 , H01L21/02505 , H01L21/0254 , H01L21/02642 , H01L21/02647 , H01L29/2003 , H01L29/267
摘要： A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate and forms a first aluminum (Al)-containing film in compression overlying the Si substrate. Nano-column holes are formed in the first Al-containing film, which exposes regions of the underlying Si substrate. A layer of GaN layer is selectively grown from the exposed regions, covering the first Al-containing film. The GaN is grown using a lateral nanoheteroepitaxy overgrowth (LNEO) process. The above-mentioned processes are reiterated, forming a second Al-containing film in compression, forming nano-column holes in the second Al-containing film, and selectively growing a second GaN layer. Film materials such as Al2O3, Si1-xGex, InP, GaP, GaAs, AlN, AlGaN, or GaN, may be initially grown at a low temperature. By increasing the growth temperatures, a compressed layer of epitaxial GaN can be formed on a Si substrate.
摘要翻译：提供了一种在硅（Si）和氮化镓（GaN）膜之间形成匹配的热膨胀界面的方法。该方法提供（111）Si衬底并且在压缩覆盖Si衬底上形成第一含铝（Al）的膜。在第一含Al膜中形成纳米柱孔，其暴露下面的Si衬底的区域。从暴露区域选择性地生长GaN层，覆盖第一含Al膜。使用横向纳米外延生长（LNEO）工艺生长GaN。重复上述过程，在压缩中形成第二含Al膜，在第二含Al膜中形成纳米柱孔，并选择性地生长第二GaN层。可以最初在低温下生长诸如Al 2 O 3 3，Si 1-x Ge x，InP，GaP，GaAs，AlN，AlGaN或GaN的膜材料。通过增加生长温度，可以在Si衬底上形成外延GaN的压缩层。

19. 发明授权

US07351995B2 Floating body germanium phototransistor having a photo absorption threshold bias region 有权
标题翻译：具有光吸收阈值偏置区域的浮体锗光电晶体管
公开(公告)号：US07351995B2
公开(公告)日：2008-04-01
申请号：US11894938
申请日：2007-08-22
申请人： Sheng Teng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet
发明人： Sheng Teng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet
IPC分类号： H01L29/06 , H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/062 , H01L31/113 , H01L31/0232
CPC分类号： H01L31/1136
摘要： A floating body germanium (Ge) phototransistor with a photo absorption threshold bias region, and an associated fabrication process are presented. The method includes: providing a p-doped Silicon (Si) substrate; selectively forming an insulator layer overlying a first surface of the Si substrate; forming an epitaxial Ge layer overlying the insulator layer; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers; forming source/drain (S/D) regions in the Ge layer; and, forming a photo absorption threshold bias region in the Ge layer, adjacent the channel region. In one aspect, the second S/D region has a length, longer than the first S/D length. The photo absorption threshold bias region underlies the second S/D region. Alternately, the second S/D region is separated from the channel by an offset, and the photo absorption threshold bias region is the offset in the Ge layer, after a light p-doping.
摘要翻译：提出了具有光吸收阈值偏置区域的浮体锗（Ge）光电晶体管，以及相关的制造工艺。该方法包括：提供p掺杂硅（Si）衬底; 选择性地形成覆盖在所述Si衬底的第一表面上的绝缘体层; 形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成栅极电介质，栅电极和栅极间隔物; 在Ge层中形成源极/漏极（S / D）区域; 并且在Ge层中形成邻近沟道区的光吸收阈值偏置区域。在一个方面，第二S / D区域具有比第一S / D长度更长的长度。光吸收阈值偏置区域位于第二S / D区域的下方。或者，第二S / D区域与沟道分离偏移，光吸收阈值偏置区域是在光p掺杂之后的Ge层中的偏移。

20. 发明授权

US06720258B2 Method of fabricating a nickel silicide on a substrate 有权
标题翻译：在衬底上制造硅化镍的方法
公开(公告)号：US06720258B2
公开(公告)日：2004-04-13
申请号：US10319313
申请日：2002-12-12
申请人： Jer-shen Maa , Douglas J. Tweet , Yoshi Ono , Fengyan Zhang , Sheng Teng Hsu
发明人： Jer-shen Maa , Douglas J. Tweet , Yoshi Ono , Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L2144
CPC分类号： H01L21/28518 , H01L29/456
摘要： An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.
摘要翻译：集成电路器件及其制造方法包括在（100）Si上的外延硅化镍，或者由钴中间层制造的在非晶Si上的稳定的硅化镍。在一个实施方案中，该方法包括在硅化反应之前在Ni和Si层之间沉积钴（Co）界面层。钴中间层通过由钴中间层与镍和硅的反应形成的钴/镍/硅合金层调节Ni原子的通量，使得Ni原子以相似的速率到达Si界面，即没有任何取向偏好，从而形成均匀的硅化镍层。可以将镍硅化物退火以形成均匀的结晶二硅化镍。因此，实现了（100）Si或非晶Si上的单晶硅化镍，其中硅化镍具有改进的稳定性并可用于超浅结结器件中。

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