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11. 发明授权

US07994816B1 Multiple data rate memory interface architecture 有权
标题翻译：多数据速率存储器接口架构
公开(公告)号：US07994816B1
公开(公告)日：2011-08-09
申请号：US12368308
申请日：2009-02-10
申请人： Andy L. Lee , Brian D. Johnson
发明人： Andy L. Lee , Brian D. Johnson
IPC分类号： H03K19/173
CPC分类号： G11C7/10 , H03K19/17744
摘要： The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.
摘要翻译：本发明提供了一种用于在可编程逻辑器件中实现高速多数据速率接口架构的DQS总线。 DQS总线在至少一个数据选通电路和多个I / O寄存器块之间具有平衡树结构。

12. 发明授权

US07535275B1 High-performance memory interface circuit architecture 有权
标题翻译：高性能存储器接口电路架构
公开(公告)号：US07535275B1
公开(公告)日：2009-05-19
申请号：US11789598
申请日：2007-04-24
申请人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
发明人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
IPC分类号： H03L7/00
CPC分类号： H03L7/0812 , G11C7/22 , G11C7/222 , H03L7/0805
摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
摘要翻译：可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略相移控制设置，以产生精细的相移控制设置。粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

13. 发明授权

US07323903B1 Soft core control of dedicated memory interface hardware in a programmable logic device 有权
标题翻译：可编程逻辑器件中专用存储器接口硬件的软核控制
公开(公告)号：US07323903B1
公开(公告)日：2008-01-29
申请号：US11530708
申请日：2006-09-11
申请人： Andy L. Lee , Brian D. Johnson
发明人： Andy L. Lee , Brian D. Johnson
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , G11C7/10 , H03K19/17744
摘要： The present invention is directed to a soft core logic circuit implemented in a PLD that estimates an appropriate phase delay and applies the phase shift to a read strobe signal to align its rising and falling edges at the center of a data sampling window associated with a group of read data signals. The soft core logic circuit dynamically determines an appropriate phase-shift value for the read strobe signal and adjusts the phase-shift to accommodate the environmental changes. The soft core logic circuit also introduces into the PLD various intermediate signals from a phase-shift estimator and a programmable phase delay chain.
摘要翻译：本发明涉及在PLD中实现的软核逻辑电路，其估计适当的相位延迟并将相移施加到读选通信号，以将其上升沿和下降沿对准在与组相关联的数据采样窗口的中心的读数据信号。软核心逻辑电路动态地确定读选通信号的适当相移值，并调整相移以适应环境变化。软核逻辑电路还将来自相移估计器和可编程相位延迟链的各种中间信号引入到PLD中。

14. 发明授权

US07176714B1 Multiple data rate memory interface architecture 有权
标题翻译：多数据速率存储器接口架构
公开(公告)号：US07176714B1
公开(公告)日：2007-02-13
申请号：US10857396
申请日：2004-05-27
申请人： Andy L. Lee , Brian D. Johnson
发明人： Andy L. Lee , Brian D. Johnson
IPC分类号： H03K19/173 , H03K19/177 , H03K19/094 , H03K19/0175 , G06F7/38
CPC分类号： G11C7/10 , H03K19/17744
摘要： The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.
摘要翻译：本发明提供了一种用于在可编程逻辑器件中实现高速多数据速率接口架构的DQS总线。 DQS总线在至少一个数据选通电路和多个I / O寄存器块之间具有平衡树结构。

15. 发明授权

US07123051B1 Soft core control of dedicated memory interface hardware in a programmable logic device 有权
标题翻译：可编程逻辑器件中专用存储器接口硬件的软核控制
公开(公告)号：US07123051B1
公开(公告)日：2006-10-17
申请号：US10873668
申请日：2004-06-21
申请人： Andy L. Lee , Brian D. Johnson
发明人： Andy L. Lee , Brian D. Johnson
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , G11C7/10 , H03K19/17744
摘要： The present invention is directed to a soft core logic circuit implemented in a PLD that estimates an appropriate phase delay and applies the phase shift to a read strobe signal to align its rising and falling edges at the center of a data sampling window associated with a group of read data signals. The soft core logic circuit dynamically determines an appropriate phase-shift value for the read strobe signal and adjusts the phase-shift to accommodate the environmental changes. The soft core logic circuit also introduces into the PLD various intermediate signals from a phase-shift estimator and a programmable phase delay chain.
摘要翻译：本发明涉及在PLD中实现的软核逻辑电路，其估计适当的相位延迟并将相移施加到读选通信号，以将其上升沿和下降沿对准在与组相关联的数据采样窗口的中心的读数据信号。软核心逻辑电路动态地确定读选通信号的适当相移值，并调整相移以适应环境变化。软核逻辑电路还将来自相移估计器和可编程相位延迟链的各种中间信号引入到PLD中。

16. 发明授权

US06661253B1 Passgate structures for use in low-voltage applications 有权
公开(公告)号：US06661253B1
公开(公告)日：2003-12-09
申请号：US09931475
申请日：2001-08-16
申请人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
发明人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K17/063 , H03K19/177 , H03K19/1778
摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE−Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

17. 发明申请

US20090267645A1 PASSGATE STRUCTURES FOR USE IN LOW-VOLTAGE APPLICATIONS 有权
标题翻译：低电压应用中的低通滤波器结构
公开(公告)号：US20090267645A1
公开(公告)日：2009-10-29
申请号：US12484665
申请日：2009-06-15
申请人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
发明人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K17/063 , H03K19/177 , H03K19/1778
摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.
摘要翻译：提出了用于低压系统的增强型门控结构，其中Vt对单晶闸管通道通过的信号范围的影响减小。在一种布置中，通过应用较高的VGATE来提高通过NMOS通道传播的信号的VGATE-Vt极限; 在另一种布置中，Vt被降低。传统上使用单通道闸门的CMOS传动闸门的使用也被提出。

18. 发明授权

US07227395B1 High-performance memory interface circuit architecture 有权
标题翻译：高性能存储器接口电路架构
公开(公告)号：US07227395B1
公开(公告)日：2007-06-05
申请号：US11055125
申请日：2005-02-09
申请人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
发明人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
IPC分类号： H03L7/00
CPC分类号： H03L7/0812 , G11C7/22 , G11C7/222 , H03L7/0805
摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
摘要翻译：可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略相移控制设置，以产生精细的相移控制设置。粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

19. 发明授权

US08487651B2 Multiple data rate memory interface architecture 有权
公开(公告)号：US08487651B2
公开(公告)日：2013-07-16
申请号：US13176284
申请日：2011-07-05
申请人： Andy L. Lee , Brian D. Johnson
发明人： Andy L. Lee , Brian D. Johnson
IPC分类号： H03K19/173
CPC分类号： G11C7/10 , H03K19/17744
摘要： The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.

20. 发明授权

US08305121B1 High-performance memory interface circuit architecture 有权
标题翻译：高性能存储器接口电路架构
公开(公告)号：US08305121B1
公开(公告)日：2012-11-06
申请号：US13168499
申请日：2011-06-24
申请人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
发明人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
IPC分类号： H03L7/00
CPC分类号： H03L7/0812 , G11C7/22 , G11C7/222 , H03L7/0805
摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
摘要翻译：可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略相移控制设置，以产生精细的相移控制设置。粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

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