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11. 发明授权

US06434361B1 Synchronization burst processor for a processing satellite 有权
标题翻译：用于处理卫星的同步突发处理器
公开(公告)号：US06434361B1
公开(公告)日：2002-08-13
申请号：US09408261
申请日：1999-09-29
申请人： Dominic P. Carrozza , Vincent C. Moretti , David A. Wright , Gregory S. Caso
发明人： Dominic P. Carrozza , Vincent C. Moretti , David A. Wright , Gregory S. Caso
IPC分类号： H04B7185
CPC分类号： H04L7/042 , H04B7/2125
摘要： A synchronization burst processor (56) used in a processing satellite (12) in a satellite based communications system (10) is provided with a sync burst memory (72), a first double correlator (74), a second double correlator (76) and a modulus module (78). The sync burst memory (72) stores at least one sync burst (52) transmitted from a terrestrial terminal (14) to the processing satellite (12) where the sync burst (52) is formed from a quadrature pair sample set {p, q}. The first double correlator (74) performs an early correlation and a late correlation of the p samples relative to a sync burst slot (50) to generate an early correlation Pe and a late correlation Pl. The second double correlator (76) performs an early correlation and a late correlation of the q samples relative to the sync burst slot (50) to generate an early correlation Qe and a late correlation Ql. The modulus module (78) determines an early modulus Re and a late modulus Rl from the early correlations Pe and Qe and from the late correlations Pl and Ql. The early modulus Re and the late modulus Rl are used to determine if the sync burst (52) is present in the sync burst slot (50) and if the sync burst (52) is early or late relative to the sync burst slot (50).
摘要翻译：在基于卫星的通信系统（10）中的处理卫星（12）中使用的同步突发处理器（56）具有同步脉冲串存储器（72），第一双相关器（74），第二双相关器（76）和模数模块（78）。同步突发存储器（72）存储从地面终端（14）发送到处理卫星（12）的至少一个同步脉冲串（52），其中同步脉冲串（52）由正交对采样集{p，q }。第一双相关器（74）执行相对于同步突发时隙（50）的p个样本的早期相关和后期相关，以产生早期相关Pe和晚期相关性P1。第二双相关器（76）执行相对于同步脉冲串时隙（50）的q个样本的早期相关和晚期相关，以产生早期相关Qe和晚期相关Q1。模量模块（78）从早期相关性Pe和Qe以及从晚期相关性P1和Q1确定早期模量Re和后期模量R1。早期模数Re和延迟模数R1用于确定同步脉冲串（52）是否存在于同步脉冲串时隙（50）中，并且如果同步脉冲串（52）相对于同步脉冲串时隙（50）早或晚）。

12. 发明授权

US06430418B1 Method and system for controlling uplink power in a satellite communication system using error leveling 有权
标题翻译：用于使用误差调整在卫星通信系统中控制上行链路功率的方法和系统
公开(公告)号：US06430418B1
公开(公告)日：2002-08-06
申请号：US09596344
申请日：2000-06-19
申请人： Dennis A. Nivens , David A. Wright , Michael S. Munoz , Gregory S. Caso , Scott A. Stephens
发明人： Dennis A. Nivens , David A. Wright , Michael S. Munoz , Gregory S. Caso , Scott A. Stephens
IPC分类号： H04B700
CPC分类号： H04B7/18543 , H04B7/18513
摘要： A method and system for controlling uplink power in a satellite communication system using error leveling is provided. The uplink power control system for a satellite communication system of a preferred embodiment of the present invention comprises a communication satellite (101) and at least one UET (105). The communication satellite (101) includes an error detector (211) and a comparator (215). The UET (105) includes a receiver (206) for receiving an error indicator signal from the comparator (215), and a power profile processor (216) for controlling the transmit power level of the particular chanslot being used by the UET in response to the error indicator. A preferred method for controlling the transmit power level of a particular chanslot assigned to a UET in a satellite communication system in accordance with the present invention includes determining an error count for an uplink data signal received from the UET in the chanslot (403), and comparing the error count to a predetermined error threshold (404). The method further includes generating an error indicator signal for the chanslot in response to the comparison (405), and controlling the transmit power level of the particular chanslot in response to the error indicator (409, 410).
摘要翻译：提供了一种使用误差校正在卫星通信系统中控制上行链路功率的方法和系统。本发明优选实施例的用于卫星通信系统的上行链路功率控制系统包括通信卫星（101）和至少一个UET（105）。通信卫星（101）包括误差检测器（211）和比较器（215）。 UET（105）包括用于从比较器（215）接收错误指示符信号的接收器（206）和用于响应于UET而被UET使用的特定车厢的发射功率电平的功率配置文件处理器（216）错误指示器。根据本发明的用于控制分配给卫星通信系统中的UET的特定信道的发射功率电平的优选方法包括确定从信道（403）中的UET接收的上行链路数据信号的误差计数，以及将误差计数与预定误差阈值进行比较（404）。所述方法还包括响应于所述比较（405）生成所述信道的错误指示符信号，以及响应于所述错误指示符（409,410）来控制所述特定信道的发射功率电平。

13. 发明授权

US06236687B1 Decision directed phase locked loop (DD-PLL) for use with short block codes in digital communication systems 有权
标题翻译：决策导向锁相环（DD-PLL），用于数字通信系统中的短块码
公开(公告)号：US06236687B1
公开(公告)日：2001-05-22
申请号：US09258846
申请日：1999-02-26
申请人： Gregory S. Caso , David A. Wright , Dominic P. Carrozza
发明人： Gregory S. Caso , David A. Wright , Dominic P. Carrozza
IPC分类号： H03D318
CPC分类号： H04L1/0057 , H04L27/2332 , H04L2027/003 , H04L2027/0055 , H04L2027/0089
摘要： An improved digital decision directed phase locked loop (DD-PLL) for use with short block codes using phase shifting keying (PSK) modulation. The improvement involves a conventional digital phase lock loop which is modified to base its loop corrections on the results obtained by decoding the short block code rather than on a symbol by symbol basis as is customary in conventional DD-PLLs. The improved method of loop corrections involves retaining the symbol data pending the decoder's decision, derotating the retained data in accordance with the decoded result, and integrating the derotated data to form a composite estimator upon which to base the loop correction. In its preferred embodiment, the invention uses an (8, 4) biorthogonal code with quatenary PSK.
摘要翻译：改进的数字决策定向锁相环（DD-PLL），用于使用相移键控（PSK）调制的短块码。该改进涉及传统的数字锁相环，其被修改为将其循环校正基于通过解码短块码获得的结果，而不是按照传统DD-PLL中的惯例的符号依据。改进的循环校正方法涉及保留符号数据等待解码器的判定，根据解码结果对保留的数据进行解除，并且整合解旋数据以形成基于循环校正的复合估计器。在其优选实施例中，本发明使用具有四分之一PSK的（8,4）双正交码。

14. 发明授权

US06349118B1 Digital channelizer having efficient architecture for cyclic shifting and method of operation thereof 有权
标题翻译：具有用于循环移位的有效结构的数字信道化及其操作方法
公开(公告)号：US06349118B1
公开(公告)日：2002-02-19
申请号：US09258847
申请日：1999-02-26
申请人： Gregory S. Caso , Vincent C. Moretti
发明人： Gregory S. Caso , Vincent C. Moretti
IPC分类号： H04L2704
CPC分类号： H04L5/06
摘要： The invention is a digital channelizer and a process for dividing an input bandwidth into at least some of N channels. A digital channelizer which divides an input bandwidth into at least some of N channels in accordance with the invention includes a window presum (102); a cyclic shift (24′), coupled to the I output groups of date words, having I cyclic shift paths, each cyclic shift path being responsive to a different output group of data words to produce I output groups of data words, each cyclic shift path comprising a plurality of word shifting elements each responsive to a group of data words; and a discrete Fourier transform (26′) coupled to the I output groups of cyclically shifted data words outputted from the cyclic shift.
摘要翻译：本发明是数字信道化器和将输入带宽划分成N个信道中的至少一些信道的过程。根据本发明，将输入带宽划分为至少一些N个信道的数字信道发送器包括窗口预测（102）; 耦合到具有I循环移位路径的I个输出组的日期字的循环移位（24'），每个循环移位路径响应不同的数据字输出组以产生I个数据字组，每个循环移位路径，其包括多个字移位元件，每个字移位元件响应于一组数据字; 以及耦合到从循环移位输出的循环移位数据字的I个输出组的离散傅里叶变换（26'）。

15. 发明授权

US06515987B1 Serial to parallel conversion of data to facilitate sharing a single buffer among multiple channels 有权
标题翻译：串行到并行转换数据，以便于在多个通道之间共享单个缓冲区
公开(公告)号：US06515987B1
公开(公告)日：2003-02-04
申请号：US09239872
申请日：1999-01-29
申请人： Dominic P. Carrozza , Gregory S. Caso
发明人： Dominic P. Carrozza , Gregory S. Caso
IPC分类号： H04Q1104
CPC分类号： G06F7/785 , H04B7/18515
摘要： The invention is a receiver and a method of receiving data having a preferred application in a satellite. A receiver in accordance with the invention includes at least one memory (118, 120), each memory including an addressable storage array which stores a sequence of data samples contained in a time division multiplexed signal and outputs the stored data samples from a plurality of channels in a sequence of data groups with each data group containing a plurality of samples from one of the plurality of channels; and an outer decoder (102), responsive to data blocks with each data block containing at least one data group, which decodes the data blocks and outputs decoded data blocks.
摘要翻译：本发明是一种在卫星中接收具有优选应用的数据的接收机和方法。根据本发明的接收机包括至少一个存储器（118,120），每个存储器包括可寻址存储阵列，其存储包含在时分多路复用信号中的数据样本序列，并从多个通道输出所存储的数据样本在数据组的序列中，每个数据组包含来自多个通道之一的多个样本; 以及外部解码器（102），响应于每个数据块包含至少一个数据组的数据块，其对数据块进行解码并输出解码的数据块。

16. 发明授权

US06351759B1 Digital channelizer having efficient architecture for discrete fourier transformation and operation thereof 有权
标题翻译：数字信道化器具有用于离散傅里叶变换和其操作的有效架构
公开(公告)号：US06351759B1
公开(公告)日：2002-02-26
申请号：US09259623
申请日：1999-02-26
申请人： Vincent C. Moretti , Gregory S. Caso
发明人： Vincent C. Moretti , Gregory S. Caso
IPC分类号： G06F1714
CPC分类号： G06F17/141
摘要： The invention is an apparatus and process for performing a discrete Fourier transform and a digital channelizer which divides an input bandwidth into at least some of N channels. An apparatus for performing a discrete Fourier transform in accordance with the invention includes at least one discrete Fourier transform computation stage (304, 305′, 402, 410, 412, 414, 419), the at least one discrete Fourier transform computation stage having N inputs representing preselected frequency bands with each input containing an input signal containing real data and P actual outputs each containing an output signal, P being less than N, at least one of the P actual output signals containing a conjugate of one of the N input frequency bands; and a processing device (602, 702), coupled to at least one P actual output containing a signal which is a conjugate, which processes the conjugate as representative of one of the N input frequency bands.
摘要翻译：本发明是用于执行离散付里叶变换的装置和过程，以及将输入带宽分成至少一些N个信道的数字信道化器。根据本发明的用于执行离散付里叶变换的装置包括至少一个离散付里叶变换计算阶段（304,305'，402,410,412,414,419），所述至少一个离散付里叶变换计算阶段具有N 输入表示预选频带，每个输入包含包含实际数据的输入信号和每个包含P小于N的输出信号的P个实际输出，P个实际输出信号中的至少一个包含N个输入频率乐队以及耦合到包含作为共轭的信号的至少一个P实际输出的处理设备（602,702），其将所述共轭处理为代表N个输入频带之一。

17. 发明授权

US06701264B2 Method of and apparatus for calibrating receive path gain 有权
标题翻译：校准接收路径增益的方法和装置
公开(公告)号：US06701264B2
公开(公告)日：2004-03-02
申请号：US09918655
申请日：2001-07-31
申请人： Gregory S. Caso , Dominic P. Carrozza
发明人： Gregory S. Caso , Dominic P. Carrozza
IPC分类号： G06F1900
CPC分类号： H03M1/1014 , H03M1/12 , H04Q2213/13034 , H04Q2213/13333
摘要： An apparatus (100), and method, for calibrating gain in satellite uplink receiver electronics includes an uplink receiver, a measurement processor, and an attenuator (106). The measurement processor receives the uplink signal from the uplink receiver and includes circuitry to sample (118) the uplink signals during a blanking interval and outputs a gain calibration signal. The sampling circuitry (118) may sample uplink signals periodically or responsive to extreme changes in conditions, and may sample the uplink signal multiple times during a blanking interval to output a multiple measurement sample. The measurement processor may include averaging circuitry (124) to produce a sample average. The method and apparatus (200) may both be used with TDMA systems.
摘要翻译：用于校准卫星上行链路接收机电子设备中的增益的装置（100）和方法包括上行链路接收机，测量处理器和衰减器（106）。测量处理器从上行链路接收器接收上行链路信号，并且包括在消隐间隔期间采样（118）上行链路信号的电路并输出增益校准信号。采样电路（118）可以周期性地对上行链路信号进行采样或响应于条件的极端变化，并且可以在消隐间隔期间多次采样上行链路信号以输出多个测量样本。测量处理器可以包括平均电路（124）以产生采样平均值。所述方法和装置（200）都可以与TDMA系统一起使用。

18. 发明授权

US06393066B1 Efficient digital channelizer system and method of operation thereof 有权
标题翻译：高效数字渠道化系统及其运行方法
公开(公告)号：US06393066B1
公开(公告)日：2002-05-21
申请号：US09259029
申请日：1999-02-26
申请人： Vincent C. Moretti , Dominic P. Carrozza , Gregory S. Caso
发明人： Vincent C. Moretti , Dominic P. Carrozza , Gregory S. Caso
IPC分类号： H04L2704
CPC分类号： H04J1/08 , H04L5/06
摘要： The invention is a digital channelizer and a process for dividing an input bandwidth into at least some of N channels. A digital channelizer which divides an input bandwidth into at least some of N channels in accordance with the invention includes an analog to digital converter (14); a demultiplexer (16), coupled to the analog to digital converter, a window presum (102) having N outputs, coupled to the parallel data streams, each output being a function of a window presum function and data words from a plurality of the parallel data streams; and a cyclic shift (24′), coupled to I output groups of data words.
摘要翻译：本发明是数字信道化器和将输入带宽划分成N个信道中的至少一些信道的过程。根据本发明的将输入带宽划分为N个信道中的至少一些的数字信道化器包括模数转换器（14）; 耦合到所述模数转换器的解复用器（16），具有N个输出的窗口（102），耦合到所述并行数据流，每个输出是窗口推定函数的函数，以及来自多个并行的数据字数据流以及耦合到I个输出数据字组的循环移位（24'）。

19. 发明授权

US06330287B1 Digital channelizer having efficient architecture for window presum using distributed arithmetic for providing window presum calculations in one clock cycle 有权
标题翻译：数字信道化器具有使用分布式算法的窗口高效架构，用于在一个时钟周期内提供窗口预测计算
公开(公告)号：US06330287B1
公开(公告)日：2001-12-11
申请号：US09259030
申请日：1999-02-26
申请人： Gregory S. Caso , Vincent C. Moretti
发明人： Gregory S. Caso , Vincent C. Moretti
IPC分类号： H04L2704
CPC分类号： G06F17/141
摘要： A digital channelizer and a process for dividing input bandwidth into at least some of N channels are disclosed. The digital channelizer which divides an input bandwidth into at least some of N channels in accordance with the invention includes an analog to digital converter (14), a demodulator (16) coupled to the analog to digital converter, a window presum (102) coupled to the parallel streams of data words and a discrete Fourier transform apparatus (26′), coupled to the N outputs of the window presum, having N inputs and which performs a discrete Fourier transform on the N inputs to output at least some of the N channels.
摘要翻译：公开了一种将输入带宽划分成N个信道中的至少一些的数字信道化器和处理。根据本发明，将输入带宽划分为N个信道中的至少一些的数字信道化器包括模数转换器（14），耦合到模数转换器的解调器（16），耦合到模拟数字转换器到数据字的并行流和离散傅立叶变换装置（26'），其耦合到具有N个输入的窗口的N个输出，并且在N个输入上执行离散傅里叶变换以输出N个输入中的至少一些频道

20. 发明授权

US06263195B1 Wideband parallel processing digital tuner 有权
标题翻译：宽带并行处理数字调谐器
公开(公告)号：US06263195B1
公开(公告)日：2001-07-17
申请号：US09249904
申请日：1999-02-12
申请人： Edward L. Niu , Sam H. Liu , Gregory S. Caso
发明人： Edward L. Niu , Sam H. Liu , Gregory S. Caso
IPC分类号： H03K900
CPC分类号： H04B1/28 , H04B1/00
摘要： A wideband digital tuner (14′) has an analog front-end section (10), a high speed analog-to-digital converter (12), demultiplexer (13) and a plurality of filters (341-342) arranged in a parallel input architecture to process wideband digital data received at extremely high sampling rates, such as at 2 Gsps (giga-samples per second). The tuner greatly attenuates an undesired spectral half of the wide bandwidth digital spectrum of the incoming digital signal using a complex band-pass filter, such as a Hilbert Transform filter. The tuner places the remaining half of the wide bandwidth digital spectrum of the incoming digital signal at complex baseband and down samples by 2. The architecture of the tuner can be partitioned into two separate halves which are hardware copies of each other.
摘要翻译：宽带数字调谐器（14'）具有模拟前端部分（10），高速模数转换器（12），解复用器（13）和并联布置的多个滤波器（341-342）输入架构来处理以非常高的采样率接收的宽带数字数据，例如2 Gsps（千兆比特每秒）。调谐器使用诸如希尔伯特变换滤波器的复带通滤波器大大地衰减输入数字信号的宽带数字频谱的不希望的频谱一半。调谐器将输入数字信号的宽带数字频谱的剩余一半放置在复杂的基带和下采样中。调谐器的架构可以分为两个分开的两个，这两个是相互的硬件副本。

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