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11. 发明授权

US08236710B2 Technique to create a buried plate in embedded dynamic random access memory device 有权
标题翻译：在嵌入式动态随机存取存储器件中创建掩埋板的技术
公开(公告)号：US08236710B2
公开(公告)日：2012-08-07
申请号：US12899638
申请日：2010-10-07
申请人： Ashima B. Chakravarti , Jacob B. Dadson , Paul J. Higgins , Babar A. Khan , John J. Moore , Christopher C. Parks , Rohit S. Takalkar
发明人： Ashima B. Chakravarti , Jacob B. Dadson , Paul J. Higgins , Babar A. Khan , John J. Moore , Christopher C. Parks , Rohit S. Takalkar
IPC分类号： H01L21/76
CPC分类号： H01L27/10867 , H01L29/66181 , H01L29/945 , Y10S438/957
摘要： A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.
摘要翻译：为诸如DRAM器件的半导体和/或存储器件提供了用于形成沟槽结构的方法。在一个实施例中，用于形成沟槽结构的方法包括在半导体衬底中形成沟槽，并且将沟槽的侧壁暴露于含砷气体以在沟槽的侧壁上吸附含砷层。然后将材料层沉积在沟槽的侧壁上以将含砷层包封在材料层和沟槽的侧壁之间。

12. 发明申请

US20100038751A1 STRUCTURE AND METHOD FOR MANUFACTURING TRENCH CAPACITANCE 有权
标题翻译：用于制造TRENCH电容的结构和方法
公开(公告)号：US20100038751A1
公开(公告)日：2010-02-18
申请号：US12191430
申请日：2008-08-14
申请人： HUILONG ZHU , Babar A. Khan , Xi Li , Joyce C. Liu , Thomas A. Wallner
发明人： HUILONG ZHU , Babar A. Khan , Xi Li , Joyce C. Liu , Thomas A. Wallner
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L29/66181 , H01L27/10861
摘要： A deep trench (DT) capacitor comprises a trench in a silicon layer, a buried plate surrounding the trench, a dielectric layer lining the trench, and a node conductor in the trench. The top surface of the poly node is higher than the surface of the silicon layer, so that it is high enough to ensure that a nitride liner used as a CMP etch stop for STI oxide surrounding a top portion of the poly node will be higher than the STI oxide, so that the nitride liner can be removed prior to forming a silicide contact on top of the poly node.
摘要翻译：深沟槽（DT）电容器包括硅层中的沟槽，围绕沟槽的掩埋板，衬套沟槽的电介质层和沟槽中的节点导体。多晶硅节点的顶表面高于硅层的表面，使得其足够高以确保用作CMP蚀刻的氮化物衬垫停止用于围绕多晶硅节点的顶部的STI氧化物将高于 STI氧化物，使得氮化物衬垫可以在在多晶硅节点的顶部形成硅化物接触之前被去除。

13. 发明授权

US06507511B1 Secure and dense SRAM cells in EDRAM technology 失效
标题翻译： EDRAM技术中的安全且密集的SRAM单元
公开(公告)号：US06507511B1
公开(公告)日：2003-01-14
申请号：US09969360
申请日：2001-10-02
申请人： John E. Barth, Jr. , Subramanian S. Iyer , Babar A. Khan , Robert C. Wong
发明人： John E. Barth, Jr. , Subramanian S. Iyer , Babar A. Khan , Robert C. Wong
IPC分类号： G11C1124
CPC分类号： G11C11/4125
摘要： Addition of capacitance to the storage nodes of static random access memory cells and other types of integrated circuits substantially increases Qcrit and substantially eliminates soft errors due to alpha particles; susceptibility to which would otherwise increase as integrated circuits are scaled to smaller sizes and manufactured at increased integration densities. Formation of the added capacitance as deep trench capacitors avoids any constraint on circuit or memory cell layout. Degradation of performance is avoided and performance potentially improved by permitting alteration of proportions of pull-down and pass gate transistors in view of the increased stability imparted by the added capacitors. One of the capacitor electrodes is preferably shorted to the supply voltage through an impurity well. Thus, the memory cell size can be reduced while greatly reducing susceptibility to soft errors; contrary to the effects of scaling at current and foreseeable feature size regimes.
摘要翻译：向静态随机存取存储器单元和其他类型的集成电路的存储节点增加电容大大增加了Qcrit并且基本消除了由于α粒子引起的软错误; 随着集成电路被缩放到更小的尺寸并且以增加的集成密度制造，易受性将随之增加。形成作为深沟槽电容器的附加电容避免了对电路或存储器单元布局的任何限制。鉴于增加的电容器增加的稳定性，可以通过允许下拉和栅极晶体管的比例的改变来避免性能的降低和性能的提高。电容器电极之一优选通过杂质井短路到电源电压。因此，可以减小存储单元尺寸，同时大大降低对软错误的敏感性; 与当前和可预见的特征尺寸体系的缩放效应相反。

14. 发明授权

US5596431A Plasma addressed liquid crystal display with etched electrodes 失效
标题翻译：带蚀刻电极的等离子体寻址液晶显示器
公开(公告)号：US5596431A
公开(公告)日：1997-01-21
申请号：US413052
申请日：1995-03-29
申请人： Petrus F. G. Bongaerts , Jacob Bruinink , Adrianus L. J. Burgmans , Henri R. J. R. Van Helleputte , Babar A. Khan , Karel E. Kuijk
发明人： Petrus F. G. Bongaerts , Jacob Bruinink , Adrianus L. J. Burgmans , Henri R. J. R. Van Helleputte , Babar A. Khan , Karel E. Kuijk
IPC分类号： G02F1/1333 , G02F1/133 , G02F1/1345 , G09F9/35 , H01J17/04 , H05K3/10 , G02F1/13 , G09G3/22
CPC分类号： G02F1/13334 , H05K3/107
摘要： A method for making an electrical device such as a PALC display device, and the electrical device or PALC device so made, in which a channel plate is provided with substantially vertical side walls, and the electrodes are formed by a self-aligning anisotropic plasma etching process which requires no photolithography. A similar process may be used to form a fanout region for individual contacting of channel electrodes. For improved contacting, preferably the fanout region is also channelled and an upstanding structure such as columns provided in the fanout channels so that the spaces between the columns and between the columns and the side walls are filled up with deposited metal that remains following the anisotropic etching process.
摘要翻译：一种用于制造诸如PALC显示装置的电气装置的方法，以及如此制造的电气装置或PALC装置，其中通道板设置有基本上垂直的侧壁，并且电极通过自对准各向异性等离子体蚀刻不需要光刻的工艺。可以使用类似的过程来形成用于沟道电极的单独接触的扇出区域。为了改善接触，优选地，扇出区也被引导，并且在扇出通道中设置直立结构，例如柱，使得柱之间和柱与侧壁之间的空间被填充有保留在各向异性蚀刻之后的沉积金属处理。

15. 发明授权

US09064744B2 Structure and method to realize conformal doping in deep trench applications 有权
标题翻译：在深沟槽应用中实现适形掺杂的结构和方法
公开(公告)号：US09064744B2
公开(公告)日：2015-06-23
申请号：US13562779
申请日：2012-07-31
申请人： Veeraraghavan S. Basker , Hemanth Jagannathan , Sivananda Kanakasabapathy , Babar A. Khan
发明人： Veeraraghavan S. Basker , Hemanth Jagannathan , Sivananda Kanakasabapathy , Babar A. Khan
IPC分类号： H01L21/8242 , H01L27/12 , H01L27/108 , H01L21/225
CPC分类号： H01L27/1211 , H01L21/0243 , H01L21/02532 , H01L21/2253 , H01L21/2256 , H01L27/10861 , H01L27/10894
摘要： The specification and drawings present a new method, ASIC and computer/software related product (e.g., a computer readable memory) are presented for realizing conformal doping in embedded deep trench applications in the ASIC. A common SOI substrate with intrinsic or low dopant concentration is used for manufacturing such ASICs comprising a logic area having MOSFETs utilizing, for example, ultra thin body and box technology and an eDRAM area having deep trench capacitors with the conformal doping.
摘要翻译：说明书和附图提出了一种新的方法，ASIC和计算机/软件相关产品（例如，计算机可读存储器）被呈现用于在ASIC中的嵌入式深沟槽应用中实现适形掺杂。具有本征或低掺杂浓度的普通SOI衬底用于制造这样的ASIC，其包括具有利用例如超薄体和盒技术的MOSFET的逻辑区域和具有适形掺杂的深沟槽电容器的eDRAM区域。

16. 发明授权

US08779490B2 DRAM with dual level word lines 有权
标题翻译： DRAM具有双电平字线
公开(公告)号：US08779490B2
公开(公告)日：2014-07-15
申请号：US13551766
申请日：2012-07-18
申请人： Babar A. Khan , Effendi Leobandung
发明人： Babar A. Khan , Effendi Leobandung
IPC分类号： H01L27/108 , H01L29/94 , H01L29/66 , H01L21/8242 , H01L21/336 , H01L21/8234
CPC分类号： H01L27/10867 , H01L21/84 , H01L27/0207 , H01L27/10891 , H01L27/1203 , H01L29/945
摘要： A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels.
摘要翻译：深沟槽电容器上的顶部半导体层和导电帽结构通过蚀刻同时构图。导电盖结构的每个图案化部分构成导电盖结构，其横向接触作为顶部半导体层的图案化剩余部分之一的半导体材料部分。栅电极形成为不互连的离散结构。在接触电介质层的形成和平坦化之后，通过栅极线形成在接触电介质层上方的线路电平以提供与栅电极的电连接。彼此电连接的栅极电极和通过栅极线构成跨越两个电平存在的栅极线。

17. 发明申请

US20130285193A1 METAL-INSULATOR-METAL (MIM) CAPACITOR WITH DEEP TRENCH (DT) STRUCTURE AND METHOD IN A SILICON-ON-INSULATOR (SOI) 有权
公开(公告)号：US20130285193A1
公开(公告)日：2013-10-31
申请号：US13457601
申请日：2012-04-27
申请人： John E. Barth, JR. , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson
发明人： John E. Barth, JR. , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L28/40 , H01L21/84 , H01L27/1203 , H01L28/91 , H01L29/66181 , H01L29/945
摘要： A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.

18. 发明申请

US20120086103A1 TECHNIQUE TO CREATE A BURIED PLATE IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE 有权
标题翻译：在嵌入式动态随机访问存储器件中创建一个平板的技术
公开(公告)号：US20120086103A1
公开(公告)日：2012-04-12
申请号：US12899638
申请日：2010-10-07
申请人： ASHIMA B. CHAKRAVARTI , Jacob B. Dadson , Paul J. Higgins , Babar A. Khan , John J. Moore , Christopher C. Parks , Rohit S. Takalkar
发明人： ASHIMA B. CHAKRAVARTI , Jacob B. Dadson , Paul J. Higgins , Babar A. Khan , John J. Moore , Christopher C. Parks , Rohit S. Takalkar
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L27/10867 , H01L29/66181 , H01L29/945 , Y10S438/957
摘要： A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.
摘要翻译：为诸如DRAM器件的半导体和/或存储器件提供了用于形成沟槽结构的方法。在一个实施例中，用于形成沟槽结构的方法包括在半导体衬底中形成沟槽，并且将沟槽的侧壁暴露于含砷气体以在沟槽的侧壁上吸附含砷层。然后将材料层沉积在沟槽的侧壁上以将含砷层包封在材料层和沟槽的侧壁之间。

19. 发明授权

US06670675B2 Deep trench body SOI contacts with epitaxial layer formation 有权
公开(公告)号：US06670675B2
公开(公告)日：2003-12-30
申请号：US09922892
申请日：2001-08-06
申请人： Herbert L. Ho , S. Sundar K. Iyer , Babar A. Khan , Robert Hannon
发明人： Herbert L. Ho , S. Sundar K. Iyer , Babar A. Khan , Robert Hannon
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L29/78603 , H01L29/78612
摘要： A silicon-on-insulation (SOI) body contact is formed within a device region of an SOI substrate so that no space of the SOI substrate is wasted for implementing a body contact. The body contact is formed by epitaxially growing silicon and depositing polysilicon. An electrical device can be formed to overlie the body contact. Thus, no additional circuitry or conductive path is required to electrically connect a body contact and a device region. Also, the body contact provides a predictable electrical characteristics without sacrificing the benefits attained from using the SOI substrate and conservation surface space on the semiconductor die.

20. 发明授权

US06433471B1 Plasma addressed liquid crystal display with glass spacers 失效
标题翻译：等离子体寻址液晶显示屏与玻璃间隔
公开(公告)号：US06433471B1
公开(公告)日：2002-08-13
申请号：US08588800
申请日：1996-01-19
申请人： Babar A. Khan , Henri R. J. R. Van Helleputte , Adrianus L. J. Burgmans , Karel Elbert Kuijk , Petrus F. G. Bongaerts , Jacob Bruinink , Thomas Stanley Buzak , Kevin John Ilcisin , Paul Christopher Martin
发明人： Babar A. Khan , Henri R. J. R. Van Helleputte , Adrianus L. J. Burgmans , Karel Elbert Kuijk , Petrus F. G. Bongaerts , Jacob Bruinink , Thomas Stanley Buzak , Kevin John Ilcisin , Paul Christopher Martin
IPC分类号： H01J162
CPC分类号： G02F1/13334 , G02F1/13394
摘要： A flat display device, preferably of the PALC type, in which the plasma channels are formed by etching laterally-spaced slots in a spacer plate, attaching a thin dielectric sheet over the etched spacer plate, and bonding the etched spacer plate to a transparent substrate such that each channel is formed by the portion of the substrate between flanking walls formed by the etched slots in the spacer plate, adjacent flanking walls in the spacer plate, and the overlying portion of the thin dielectric sheet. In a modification, strengthening crossbars are formed between adjacent flanking walls.
摘要翻译：优选为PALC型的平面显示装置，其中通过在间隔板中蚀刻横向间隔开的狭缝形成等离子体通道，将薄的电介质薄片附着在蚀刻的间隔板上，并将蚀刻的间隔板结合到透明基板使得每个通道由衬底的部分由间隔板中的蚀刻槽形成的侧壁之间，间隔板中相邻的侧壁和薄介电片的上部形成。在一个修改中，在相邻侧壁之间形成加强横梁。

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