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11. 发明申请

US20090219761A1 CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE 有权
标题翻译：存储设备编程期间的费用损失补偿
公开(公告)号：US20090219761A1
公开(公告)日：2009-09-03
申请号：US12177972
申请日：2008-07-23
申请人： Violante Moschiano , Michele Incarnati , Giovanni Santin , Danilo Orlandi
发明人： Violante Moschiano , Michele Incarnati , Giovanni Santin , Danilo Orlandi
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454
摘要： A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation.
摘要翻译：所选字线上的所选择的存储单元通过增加阶跃电压的多个编程脉冲进行编程。在成功的程序验证操作之后，所选存储单元的编程被禁止，同时所选字线的其它存储单元被编程。对所选存储单元执行另一个程序验证操作。如果程序验证操作失败，则耦合到所选单元的位线被偏置在阶跃电压上，并且向所选择的字线发出最终的编程脉冲。然后，所选择的存储单元被锁定以进一步编程，而不评估最终程序验证操作。

12. 发明申请

US20120287726A1 ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING 有权
标题翻译：用于存储器编程的架构和方法
公开(公告)号：US20120287726A1
公开(公告)日：2012-11-15
申请号：US13561248
申请日：2012-07-30
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
IPC分类号： G11C7/00
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译：例如，公开了存储器，存储器件和系统的编程方法。在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。

13. 再颁专利

USRE43665E1 Reading non-volatile multilevel memory cells 有权
公开(公告)号：USRE43665E1
公开(公告)日：2012-09-18
申请号：US13268049
申请日：2011-10-07
申请人： Violante Moschiano , Giovanni Santin , Michele Incarnati
发明人： Violante Moschiano , Giovanni Santin , Michele Incarnati
IPC分类号： G11C16/00
CPC分类号： G11C16/3418
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes receiving a request to read data stored in a first cell of a first word line, performing a read operation on an adjacent cell of a second word line in response to the request, determining whether the first cell is in a disturbed condition based on the read operation. The method includes reading data stored in the first cell in response to the read request by applying a read reference voltage to the first word line and adjusting a sensing parameter if the first cell is in the disturbed condition.

14. 发明授权

US08130542B2 Reading non-volatile multilevel memory cells 有权
标题翻译：读取非易失性多层存储单元
公开(公告)号：US08130542B2
公开(公告)日：2012-03-06
申请号：US12701085
申请日：2010-02-05
申请人： Violante Moschiano , Giovanni Santin , Michele Incarnati
发明人： Violante Moschiano , Giovanni Santin , Michele Incarnati
IPC分类号： G11C16/00
CPC分类号： G11C16/3418
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes receiving a request to read data stored in a first cell of a first word line, performing a read operation on an adjacent cell of a second word line in response to the request, determining whether the first cell is in a disturbed condition based on the read operation. The method includes reading data stored in the first cell in response to the read request by applying a read reference voltage to the first word line and adjusting a sensing parameter if the first cell is in the disturbed condition.
摘要翻译：本公开的实施例提供用于读取非易失性多级存储器单元的方法，设备，模块和系统。一种方法包括接收读取存储在第一字线的第一单元中的数据的请求，响应于该请求对第二字线的相邻单元执行读取操作，确定第一单元是否处于基于干扰状态对读操作。该方法包括：如果第一单元处于干扰状态，则通过将读取参考电压施加到第一字线并调整感测参数来读取响应于读取请求而存储在第一单元中的数据。

15. 发明授权

US07995395B2 Charge loss compensation during programming of a memory device 有权
标题翻译：存储器件编程期间的充电损耗补偿
公开(公告)号：US07995395B2
公开(公告)日：2011-08-09
申请号：US12795764
申请日：2010-06-08
申请人： Violante Moschiano , Michele Incarnati , Giovanni Santin , Danilo Orlandi
发明人： Violante Moschiano , Michele Incarnati , Giovanni Santin , Danilo Orlandi
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454
摘要： A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation.
摘要翻译：所选字线上的所选择的存储单元通过增加阶跃电压的多个编程脉冲进行编程。在成功的程序验证操作之后，所选存储单元的编程被禁止，同时所选字线的其它存储单元被编程。对所选存储单元执行另一个程序验证操作。如果程序验证操作失败，则耦合到所选单元的位线被偏置在阶跃电压上，并且向所选择的字线发出最终的编程脉冲。然后，所选择的存储单元被锁定以进一步编程，而不评估最终程序验证操作。

16. 发明申请

US20100091582A1 ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING 有权
标题翻译：用于存储器编程的架构和方法
公开(公告)号：US20100091582A1
公开(公告)日：2010-04-15
申请号：US12365589
申请日：2009-02-04
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译：例如，公开了存储器，存储器件和系统的编程方法。在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。

17. 发明授权

US08879329B2 Program verify operation in a memory device 有权
标题翻译：在存储设备中进行程序验证操作
公开(公告)号：US08879329B2
公开(公告)日：2014-11-04
申请号：US12949876
申请日：2010-11-19
申请人： Violante Moschiano , Giovanni Santin , Michele Incarnati
发明人： Violante Moschiano , Giovanni Santin , Michele Incarnati
IPC分类号： G11C11/34 , G11C16/06 , G11C16/34 , G11C11/56
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/26
摘要： Methods for program verifying, program verify circuits, and memory devices are disclosed. One such method for program verifying includes generating a ramped voltage for a plurality of count values. The ramped voltage is applied to a control gate of a memory cell being program verified. At least a portion of each count value is compared to an indication of a target threshold voltage for the memory cell. When the at least a portion of the count value is equal to the indication of the target threshold voltage indication, sense circuitry is used to check if the memory cell has been activated by the voltage generated by the count. If the memory cell has been activated, an inhibit latch is set to inhibit further programming of the memory cell. If the memory cell has not been activated by the voltage, the memory cell is biased with another programming pulse.
摘要翻译：公开了用于程序验证，程序验证电路和存储器件的方法。用于程序验证的一种这样的方法包括为多个计数值生成斜坡电压。斜坡电压被施加到被程序验证的存储器单元的控制栅极。将每个计数值的至少一部分与存储器单元的目标阈值电压的指示进行比较。当计数值的至少一部分等于目标阈值电压指示的指示时，感测电路用于检查存储器单元是否已被计数产生的电压激活。如果存储单元已被激活，则设置禁止锁存器以禁止存储器单元的进一步编程。如果存储单元没有被电压激活，则存储单元被另一编程脉冲偏置。

18. 发明申请

US20120127794A1 PROGRAM VERIFY OPERATION IN A MEMORY DEVICE 有权
标题翻译：存储器件中的程序验证操作
公开(公告)号：US20120127794A1
公开(公告)日：2012-05-24
申请号：US12949876
申请日：2010-11-19
申请人： Violante Moschiano , Giovanni Santin , Michele Incarnati
发明人： Violante Moschiano , Giovanni Santin , Michele Incarnati
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/26
摘要： Methods for program verifying, program verify circuits, and memory devices are disclosed. One such method for program verifying includes generating a ramped voltage for a plurality of count values. The ramped voltage is applied to a control gate of a memory cell being program verified. At least a portion of each count value is compared to an indication of a target threshold voltage for the memory cell. When the at least a portion of the count value is equal to the indication of the target threshold voltage indication, sense circuitry is used to check if the memory cell has been activated by the voltage generated by the count. If the memory cell has been activated, an inhibit latch is set to inhibit further programming of the memory cell. If the memory cell has not been activated by the voltage, the memory cell is biased with another programming pulse.
摘要翻译：公开了用于程序验证，程序验证电路和存储器件的方法。用于程序验证的一种这样的方法包括为多个计数值生成斜坡电压。斜坡电压被施加到被程序验证的存储器单元的控制栅极。将每个计数值的至少一部分与存储器单元的目标阈值电压的指示进行比较。当计数值的至少一部分等于目标阈值电压指示的指示时，感测电路用于检查存储器单元是否已被计数产生的电压激活。如果存储单元已被激活，则设置禁止锁存器以禁止存储器单元的进一步编程。如果存储单元没有被电压激活，则存储单元被另一编程脉冲偏置。

19. 发明申请

US20110255344A1 CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE 有权
标题翻译：存储设备编程期间的费用损失补偿
公开(公告)号：US20110255344A1
公开(公告)日：2011-10-20
申请号：US13173171
申请日：2011-06-30
申请人： Violante Moschiano , Michele Incarnati , Giovanni Santin , Danilo Orlandi
发明人： Violante Moschiano , Michele Incarnati , Giovanni Santin , Danilo Orlandi
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454
摘要： A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation.
摘要翻译：所选字线上的所选择的存储单元通过增加阶跃电压的多个编程脉冲进行编程。在成功的程序验证操作之后，所选存储单元的编程被禁止，同时所选字线的其它存储单元被编程。对所选存储单元执行另一个程序验证操作。如果程序验证操作失败，则耦合到所选单元的位线被偏置在阶跃电压上，并且向所选择的字线发出最终的编程脉冲。然后，所选择的存储单元被锁定以进一步编程，而不评估最终程序验证操作。

20. 发明申请

US20100246270A1 CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE 有权
标题翻译：存储设备编程期间的费用损失补偿
公开(公告)号：US20100246270A1
公开(公告)日：2010-09-30
申请号：US12795764
申请日：2010-06-08
申请人： Violante Moschiano , Michele Incarnati , Giovanni Santin , Danilo Orlandi
发明人： Violante Moschiano , Michele Incarnati , Giovanni Santin , Danilo Orlandi
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454
摘要： A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation.
摘要翻译：所选字线上的所选择的存储单元通过增加阶跃电压的多个编程脉冲进行编程。在成功的程序验证操作之后，所选存储单元的编程被禁止，同时所选字线的其它存储单元被编程。对所选存储单元执行另一个程序验证操作。如果程序验证操作失败，则耦合到所选单元的位线被偏置在阶跃电压上，并且向所选择的字线发出最终的编程脉冲。然后，所选择的存储单元被锁定以进一步编程，而不评估最终程序验证操作。

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