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11. 发明申请

US20090201070A1 PRE-DRIVER CIRCUIT USING TRANSISTORS OF A SINGLE CHANNEL TYPE 失效
标题翻译：使用单通道晶体管的预驱动电路
公开(公告)号：US20090201070A1
公开(公告)日：2009-08-13
申请号：US12424473
申请日：2009-04-15
申请人： Christopher Wilson , Daniel Alan Berkram
发明人： Christopher Wilson , Daniel Alan Berkram
IPC分类号： H03L5/00
CPC分类号： H03K19/018528
摘要： A serial interface apparatus comprises a driver for generating a differential communication signal and a pre-driver for driving the driver circuit. The pre-driver receives an input signal that alternates between VDD and ground and produces an output signal that alternates between a lower limit that is greater than ground and an upper limit that is less than VDD. The pre-driver comprises input circuitry and actuation circuitry, and the actuation circuitry comprises transistors of a single channel type.
摘要翻译：串行接口装置包括用于产生差分通信信号的驱动器和用于驱动驱动器电路的预驱动器。预驱动器接收在VDD和地之间交替的输入信号，并产生在大于接地的下限和小于VDD的上限之间交替的输出信号。预驱动器包括输入电路和致动电路，并且致动电路包括单通道类型的晶体管。

12. 发明申请

US20090079473A1 FIFTY PERCENT DUTY CYCLE CLOCK DIVIDER CIRCUIT AND METHOD 有权
标题翻译：五分钟占空比时钟分路电路和方法
公开(公告)号：US20090079473A1
公开(公告)日：2009-03-26
申请号：US11903950
申请日：2007-09-25
申请人： Christopher Wilson , Daniel Alan Berkram
发明人： Christopher Wilson , Daniel Alan Berkram
IPC分类号： H03K21/10 , H03K23/00
CPC分类号： H03K21/10
摘要： In one embodiment, a clock divider for producing a signal having a fifty percent duty cycle includes signal modifier circuitry connected to provide a variable clock signal. Responsive to first and second control signals of the signal modifier circuitry having respective first values, the signal modifier circuitry modifies a differential clock signal that includes first and second complementary clock signals to produce the variable clock signal, which contains an extended clock phase in every Ith cycle, I being an integer. The clock divider also contains counting circuitry connected to change the value of an output signal each time I cycles of the variable clock signal are counted.
摘要翻译：在一个实施例中，用于产生具有50％占空比的信号的时钟分频器包括被连接以提供可变时钟信号的信号修改器电路。响应于具有各自的第一值的信号调节器电路的第一和第二控制信号，信号修改器电路修改包括第一和第二互补时钟信号的差分时钟信号，以产生可变时钟信号，该可变时钟信号在每隔一秒包含扩展时钟相位循环，我是一个整数。时钟分频器还包含连接的计数电路，以便在每次可变时钟信号的周期计数时改变输出信号的值。

13. 发明申请

US20080101513A1 Systems and methods for synchronizing an input signal 有权
标题翻译：用于同步输入信号的系统和方法
公开(公告)号：US20080101513A1
公开(公告)日：2008-05-01
申请号：US11588459
申请日：2006-10-27
申请人： Zhubiao Zhu , Carson Donahue Henrion , Daniel Alan Berkram
发明人： Zhubiao Zhu , Carson Donahue Henrion , Daniel Alan Berkram
IPC分类号： H04L7/00
CPC分类号： H04L7/02 , H03K3/0375 , H03K3/35613 , H03K5/135
摘要： Systems and methods for synchronizing an input signal with a substantial mitigation of race conditions and a substantial increase in resolving time are provided. One embodiment includes a system comprising a first latching device configured to latch a first output signal from the input signal and a delay element configured to receive the first output signal and output a delay signal that is a delayed version of the first output signal. The system also includes a pass-gate element configured to receive the first output signal and to output a second output signal in response to a logic state of the delay signal. The second output signal has a delayed input edge without a delayed resolving edge. The system can be configured to force the first output signal to a stable logic state in response to the first output signal having a metastable state.
摘要翻译：提供了用于同步输入信号与大量减轻竞争条件并大大增加解析时间的系统和方法。一个实施例包括一种系统，其包括被配置为从输入信号锁存第一输出信号的第一锁存装置和被配置为接收第一输出信号并输出作为第一输出信号的延迟版本的延迟信号的延迟元件。该系统还包括一个通过栅极元件，配置成接收第一输出信号并响应于延迟信号的逻辑状态输出第二输出信号。第二输出信号具有延迟的输入边沿，而没有延迟的分辨率边缘。响应于具有亚稳态的第一输出信号，该系统可被配置为迫使第一输出信号处于稳定的逻辑状态。

14. 发明申请

US20140029935A1 INDICATING A SYNCHRONIZATION POINT BETWEEN A TRANSMITTER AND A RECEIVER OF AN OPTICAL LINK 审中-公开
标题翻译：指示发射机与光链路接收器之间的同步点
公开(公告)号：US20140029935A1
公开(公告)日：2014-01-30
申请号：US13560509
申请日：2012-07-27
申请人： James Donald Regan , Peter David Maroni , Daniel Alan Berkram
发明人： James Donald Regan , Peter David Maroni , Daniel Alan Berkram
IPC分类号： H04B10/08
CPC分类号： H04L7/10 , H04L7/0331
摘要： A receiver receives a predetermined pattern over an optical link from a transmitter. In response to detecting that the predetermined pattern satisfies at least one criterion, indicating that a synchronization point has been reached to allow link training of the optical link to be performed between the transmitter and receiver.
摘要翻译：接收机通过来自发射机的光链路接收预定模式。响应于检测到预定模式满足至少一个标准，指示已经达到同步点以允许在发射机和接收机之间执行光链路的链路训练。

15. 发明授权

US08031819B2 Systems and methods for synchronizing an input signal 有权
标题翻译：用于同步输入信号的系统和方法
公开(公告)号：US08031819B2
公开(公告)日：2011-10-04
申请号：US11588459
申请日：2006-10-27
申请人： Zhubiao Zhu , Carson Donahue Henrion , Daniel Alan Berkram
发明人： Zhubiao Zhu , Carson Donahue Henrion , Daniel Alan Berkram
IPC分类号： H04L7/00
CPC分类号： H04L7/02 , H03K3/0375 , H03K3/35613 , H03K5/135
摘要： Systems and methods for synchronizing an input signal with a substantial mitigation of race conditions and a substantial increase in resolving time are provided. One embodiment includes a system comprising a first latching device configured to latch a first output signal from the input signal and a delay element configured to receive the first output signal and output a delay signal that is a delayed version of the first output signal. The system also includes a pass-gate element configured to receive the first output signal and to output a second output signal in response to a logic state of the delay signal. The second output signal has a delayed input edge without a delayed resolving edge. The system can be configured to force the first output signal to a stable logic state in response to the first output signal having a metastable state.
摘要翻译：提供了用于同步输入信号与大量减轻竞争条件并大大增加解析时间的系统和方法。一个实施例包括一种系统，其包括被配置为从输入信号锁存第一输出信号的第一锁存装置和被配置为接收第一输出信号并输出作为第一输出信号的延迟版本的延迟信号的延迟元件。该系统还包括一个通过栅极元件，配置成接收第一输出信号并响应于延迟信号的逻辑状态输出第二输出信号。第二输出信号具有延迟的输入边沿，而没有延迟的分辨率边缘。响应于具有亚稳态的第一输出信号，该系统可被配置为迫使第一输出信号处于稳定的逻辑状态。

16. 发明授权

US07715251B2 Memory access strobe configuration system and process 有权
标题翻译：内存访问选通配置系统和进程
公开(公告)号：US07715251B2
公开(公告)日：2010-05-11
申请号：US11586057
申请日：2006-10-25
申请人： Christopher Wilson , Carson D. Henrion , Daniel Alan Berkram
发明人： Christopher Wilson , Carson D. Henrion , Daniel Alan Berkram
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/04 , G11C7/222 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： A memory access strobe configuration system and process operable to generate a strobe signal having a selected phase. Based on the strobe signal, a write/read cycle using a first logic value at a memory location of a memory device generates a result logic value. The result logic value provided by the write/read cycle is compared to the first logic value. Where there is a mismatch between the result logic value and the first logic value, the phase of the strobe signal is updated. The process is then repeated using a strobe signal having the updated phase.
摘要翻译：存储器访问选通配置系统和处理，可操作以产生具有所选相位的选通信号。基于选通信号，在存储器件的存储器位置使用第一逻辑值的写/读周期生成结果逻辑值。将写/读周期提供的结果逻辑值与第一逻辑值进行比较。在结果逻辑值与第一逻辑值不匹配的情况下，更新选通信号的相位。然后使用具有更新相位的选通信号重复该过程。

17. 发明授权

US07518418B1 Ratio granularity clock divider circuit and method 有权
标题翻译：比率粒度时钟分频电路及方法
公开(公告)号：US07518418B1
公开(公告)日：2009-04-14
申请号：US11903948
申请日：2007-09-25
申请人： Christopher Wilson , Daniel Alan Berkram
发明人： Christopher Wilson , Daniel Alan Berkram
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00
CPC分类号： H03K23/68
摘要： In one embodiment, a ratio clock divider comprises circuitry for producing an input signal from a differential clock signal, part of which includes circuitry for extending a clock phase of the differential clock signal every Ith cycle to produce the input signal, I being an integer. The ratio clock divider also includes circuitry for dividing the frequency of the input signal by I to produce a divided clock signal. The divided clock signal has a frequency that equals the frequency of the differential clock signal divided by N, N being equal to I plus a fraction F.
摘要翻译：在一个实施例中，比率时钟分频器包括用于从差分时钟信号产生输入信号的电路，其中的一部分包括用于每隔一个周期扩展差分时钟信号的时钟相位以产生输入信号的电路，I为整数。比率时钟分频器还包括用于将输入信号的频率除以I以产生分频时钟信号的电路。分频时钟信号的频率等于差分时钟信号的频率除以N，N等于I加上分数F.

18. 发明申请

US20080101139A1 Memory access strobe configuration system and process 有权
标题翻译：内存访问选通配置系统和进程
公开(公告)号：US20080101139A1
公开(公告)日：2008-05-01
申请号：US11586057
申请日：2006-10-25
申请人： Christopher Wilson , Carson D. Henrion , Daniel Alan Berkram
发明人： Christopher Wilson , Carson D. Henrion , Daniel Alan Berkram
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/04 , G11C7/222 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： A memory access strobe configuration system and process operable to generate a strobe signal having a selected phase. Based on the strobe signal, a write/read cycle using a first logic value at a memory location of a memory device generates a result logic value. The result logic value provided by the write/read cycle is compared to the first logic value. Where there is a mismatch between the result logic value and the first logic value, the phase of the strobe signal is updated. The process is then repeated using a strobe signal having the updated phase.
摘要翻译：存储器访问选通配置系统和处理，可操作以产生具有所选相位的选通信号。基于选通信号，在存储器件的存储器位置使用第一逻辑值的写/读周期生成结果逻辑值。将写/读周期提供的结果逻辑值与第一逻辑值进行比较。在结果逻辑值与第一逻辑值不匹配的情况下，更新选通信号的相位。然后使用具有更新相位的选通信号重复该过程。

19. 发明申请

US20090085636A1 Pre-driver circuit and apparatus using same 有权
标题翻译：预驱动电路及其使用方法
公开(公告)号：US20090085636A1
公开(公告)日：2009-04-02
申请号：US11906010
申请日：2007-09-29
申请人： Christopher Wilson , Daniel Alan Berkram
发明人： Christopher Wilson , Daniel Alan Berkram
IPC分类号： H03L5/00
CPC分类号： H03K19/018528
摘要： In one embodiment, a pre-driver circuit comprises input circuitry connected to receive a digital input signal that alternates between an upper voltage rail and a lower voltage rail and to provide a first inverted signal that is an inversion of the digital input signal and a second inverted signal that is an inversion of the first inverted signal. The pre-driver circuit also includes actuation circuitry connected to be driven by the digital input signal, the first inverted signal, and the second inverted signal to produce a digital output signal that alternates between an upper limit that is less than the upper rail and a lower limit that is greater than the lower rail by at least an amount, wherein all transistors forming the actuation circuitry comprise a single channel type.
摘要翻译：在一个实施例中，预驱动器电路包括连接以接收数字输入信号的输入电路，所述数字输入信号在上电压轨和下电压轨之间交替，并提供作为数字输入信号反转的第一反相信号，反转信号是第一反相信号的反转。预驱动器电路还包括被连接以由数字输入信号驱动的致动电路，第一反相信号和第二反相信号，以产生数字输出信号，该数字输出信号在小于上轨道的上限和其下限大于下轨道至少一个量，其中形成致动电路的所有晶体管都包括单通道类型。

20. 发明申请

US20090079472A1 RATIO GRANULARITY CLOCK DIVIDER CIRCUIT AND METHOD 有权
标题翻译：比例粒度分时电路和方法
公开(公告)号：US20090079472A1
公开(公告)日：2009-03-26
申请号：US11903948
申请日：2007-09-25
申请人： Christopher Wilson , Daniel Alan Berkram
发明人： Christopher Wilson , Daniel Alan Berkram
IPC分类号： H03K21/10 , H03K23/00
CPC分类号： H03K23/68
摘要： In one embodiment, a ratio clock divider comprises circuitry for producing an input signal from a differential clock signal, part of which includes circuitry for extending a clock phase of the differential clock signal every Ith cycle to produce the input signal, I being an integer. The ratio clock divider also includes circuitry for dividing the frequency of the input signal by I to produce a divided clock signal. The divided clock signal has a frequency that equals the frequency of the differential clock signal divided by N, N being equal to I plus a fraction F.
摘要翻译：在一个实施例中，比率时钟分频器包括用于从差分时钟信号产生输入信号的电路，其中的一部分包括用于每隔一个周期扩展差分时钟信号的时钟相位以产生输入信号的电路，I为整数。比率时钟分频器还包括用于将输入信号的频率除以I以产生分频时钟信号的电路。分频时钟信号的频率等于差分时钟信号的频率除以N，N等于I加上分数F.

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