专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US10762019B2 Bus sharing scheme 有权
公开(公告)号：US10762019B2
公开(公告)日：2020-09-01
申请号：US15647077
申请日：2017-07-11
申请人： Cypress Semiconductor Corporation
发明人： Timothy John Williams , David G. Wright , Harold M. Kutz , Eashwar Thiagarajan , Warren S. Snyder , Mark E Hastings
IPC分类号： H03L5/00 , H01L25/00 , G06F13/40 , H03K19/173
摘要： A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of 10 pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the pads to each other.

12. 发明授权

US10666258B2 Programmable input/output circuit 有权
公开(公告)号：US10666258B2
公开(公告)日：2020-05-26
申请号：US16193261
申请日：2018-11-16
申请人： Cypress Semiconductor Corporation
发明人： Timothy John Williams , David G. Wright , Gregory John Verge , Bruce E. Byrkett
IPC分类号： H03K19/0175 , G06F5/06 , G06F12/02 , G06F13/28 , G11C16/10 , G11C7/10 , G06F13/40
摘要： A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.

13. 发明授权

US10153770B2 Programmable input/output circuit 有权
公开(公告)号：US10153770B2
公开(公告)日：2018-12-11
申请号：US15369674
申请日：2016-12-05
申请人： Cypress Semiconductor Corporation
发明人： Timothy John Williams , David G. Wright , Gregory John Verge , Bruce E. Byrkett
IPC分类号： H03K19/0175 , G11C7/10 , G06F13/28
摘要： A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.

14. 发明申请

US20170286344A1 Dynamically Reconfigurable Analog Routing and Multiplexing Architecture on a System on a Chip 审中-公开
公开(公告)号：US20170286344A1
公开(公告)日：2017-10-05
申请号：US15463703
申请日：2017-03-20
申请人： Cypress Semiconductor Corporation
发明人： Bert S. Sullam , Harold M. Kutz , Timothy John Williams , James H. Shutt , Bruce E. Byrkett , Melany Ann Richmond , Nathan Wayne Kohagen , Mark E. Hastings , Eashwar Thiagarajan , Warren S. Snyder
IPC分类号： G06F13/40
CPC分类号： G06F13/4022 , G06F2213/0038
摘要： An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined operations in response to instruction data.

15. 发明授权

US09515659B2 Programmable input/output circuit 有权
公开(公告)号：US09515659B2
公开(公告)日：2016-12-06
申请号：US14690106
申请日：2015-04-17
申请人： Cypress Semiconductor Corporation
发明人： Timothy John Williams , David G. Wright , Gregory John Verge , Bruce E. Byrkett
IPC分类号： H03K19/0175 , G06F5/06 , G06F12/02 , G06F13/28 , G11C16/10 , G06F13/40
CPC分类号： H03K19/017581 , G06F5/065 , G06F12/0246 , G06F13/28 , G06F13/4072 , G06F2212/7201 , G11C7/1057 , G11C7/1084 , G11C16/102 , H03K19/01759
摘要： A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.

16. 发明授权

US08705309B2 State-monitoring memory element 失效
标题翻译：状态监视记忆元素
公开(公告)号：US08705309B2
公开(公告)日：2014-04-22
申请号：US13915464
申请日：2013-06-11
申请人： Cypress Semiconductor Corporation
发明人： Michael Sheets , Timothy John Williams
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , H03K19/17764
摘要： Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator that the IC's state retention may be in jeopardy, possibly requiring the IC to be reset. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element. Multiple state-monitoring memory elements may be distributed in different locations on the IC for better coverage.
摘要翻译：本发明的实施例涉及一种状态监视存储元件。状态监视存储器元件可以具有比IC上的其它常规存储器元件保持逻辑状态更低的能力。因此，如果在测试期间状态监视存储器元件失败或失去状态，则可能是IC的状态保持可能存在危险的良好指示，可能需要IC复位。状态监视存储元件可以通过在二极管和/或晶体管上降低对状态监视存储元件的输入电压供应来实现。可以使用一个或多个电流源来压力状态监视存储元件。可以使用逻辑分析器来分析状态监视存储器元件的完整性，并且响应于检测状态监视存储器元件中的故障而触发IC中的适当动作，例如复位，停止，去除电源，中断。多个状态监视存储器元件可以分布在IC上的不同位置以获得更好的覆盖。

17. 发明授权

US11088692B2 Programmable input/output circuit 有权
公开(公告)号：US11088692B2
公开(公告)日：2021-08-10
申请号：US16862043
申请日：2020-04-29
申请人： Cypress Semiconductor Corporation
发明人： Timothy John Williams , David G. Wright , Gregory John Verge , Bruce E. Byrkett
IPC分类号： H03K19/0175 , G06F13/28 , G11C16/10 , G11C7/10 , G06F5/06 , G06F12/02 , G06F13/40
摘要： A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.

18. 发明授权

US11054938B2 Providing a baseline capacitance for a capacitance sensing channel 有权
公开(公告)号：US11054938B2
公开(公告)日：2021-07-06
申请号：US15659798
申请日：2017-07-26
申请人： Cypress Semiconductor Corporation
发明人： Denis Ellis , Kaveh Hosseini , Timothy John Williams , Gabriel Rowe , Roman Ogirko , Brendan Lawton
IPC分类号： G06F3/041 , G06F3/044
摘要： A capacitance-sensing circuit may include a channel input associated with measuring a capacitance of a unit cell of a capacitive sense array. The capacitance-sensing circuit may also include a capacitive hardware baseliner that is coupled to the channel input. The capacitive hardware baseliner includes a programmable baseline resistor, and a buffer with an input coupled to the programmable baseline resistor and an output coupled to the channel input. The capacitive hardware baseliner generates a baseline current based on a time constant of the channel input associated with the measuring of the capacitance of the element of the capacitive sense array using the programmable baseline resistor. The capacitive hardware baseliner provides the baseline current at the channel input to provide a charge for a sense capacitor. A change in the charge of the sense capacitor is provided by the baseline current indicating a presence of a touch object proximate to the element.

19. 发明申请

US20190214990A1 PROGRAMMABLE INPUT/OUTPUT CIRCUIT 审中-公开
公开(公告)号：US20190214990A1
公开(公告)日：2019-07-11
申请号：US16193261
申请日：2018-11-16
申请人： Cypress Semiconductor Corporation
发明人： Timothy John Williams , David G. Wright , Gregory John Verge , Bruce E. Byrkett
IPC分类号： H03K19/0175 , G11C7/10 , G11C16/10 , G06F5/06 , G06F13/28 , G06F12/02
摘要： A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.

20. 发明申请

US20170371451A1 PROVIDING A BASELINE CAPACITANCE FOR A CAPACITANCE SENSING CHANNEL 审中-公开
公开(公告)号：US20170371451A1
公开(公告)日：2017-12-28
申请号：US15659798
申请日：2017-07-26
申请人： Cypress Semiconductor Corporation
发明人： Denis Ellis , Kaveh Hosseini , Timothy John Williams , Gabriel Rowe , Roman Ogirko , Brendan Lawton
IPC分类号： G06F3/044 , G06F3/041
CPC分类号： G06F3/044 , G06F3/0416
摘要： A capacitance-sensing circuit may include a channel input associated with measuring a capacitance of a unit cell of a capacitive sense array. The capacitance-sensing circuit may also include a capacitive hardware baseliner that is coupled to the channel input. The capacitive hardware baseliner includes a programmable baseline resistor, and a buffer with an input coupled to the programmable baseline resistor and an output coupled to the channel input. The capacitive hardware baseliner generates a baseline current based on a time constant of the channel input associated with the measuring of the capacitance of the element of the capacitive sense array using the programmable baseline resistor. The capacitive hardware baseliner provides the baseline current at the channel input to provide a charge for a sense capacitor. A change in the charge of the sense capacitor is provided by the baseline current indicating a presence of a touch object proximate to the element.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式