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11. 发明授权

US5698900A Field effect transistor device with single layer integrated metal and retained semiconductor masking 失效
标题翻译：场效应晶体管器件采用单层集成金属并保留半导体掩膜
公开(公告)号：US5698900A
公开(公告)日：1997-12-16
申请号：US684734
申请日：1996-07-22
申请人： Christopher A. Bozada , Tony K. Quach , Kenichi Nakano , Gregory C. DeSalvo , G. David Via , Ross W. Dettmer , Charles K. Havasy , James S. Sewell , John L. Ebel , James K. Gillespie
发明人： Christopher A. Bozada , Tony K. Quach , Kenichi Nakano , Gregory C. DeSalvo , G. David Via , Ross W. Dettmer , Charles K. Havasy , James S. Sewell , John L. Ebel , James K. Gillespie
IPC分类号： H01L21/285 , H01L21/335 , H01L21/76 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/47 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/66462 , H01L21/28575 , H01L21/28581 , H01L21/7605 , H01L29/41775 , H01L29/42312 , H01L29/452 , H01L29/475
摘要： A periodic table group III-IV field-effect transistor device is described. The disclosed device uses a single metalization for ohmic and Schottky barrier contacts, permanent plural etch stop layers, employs a non-alloyed ohmic connection semiconductor layer and includes a permanent semiconductor material-comprised secondary mask element, a mask element which can be grown epitaxially during wafer fabrication to perform useful functions in both the device processing and device utilization environments. The device of the invention may be achieved with both an all optical lithographic process and a combined optical and electron beam lithographic process The disclosed device provides a field-effect transistor of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.
摘要翻译：描述了周期表III-IV族场效应晶体管器件。所公开的器件使用单个金属化用于欧姆和肖特基势垒触点，永久多个蚀刻停止层，采用非合金欧姆连接半导体层，并且包括具有永久性半导体材料的次级掩模元件，可以外延生长的掩模元件晶片制造以在器件处理和器件利用环境中执行有用的功能。本发明的器件可以通过全光学光刻工艺和组合的光学和电子束光刻工艺实现。所公开的器件提供了降低制造成本，增加的尺寸精度和现有技术电性能的场效应晶体管。

12. 发明授权

US06653214B1 Measured via-hole etching 失效
标题翻译：测量通孔蚀刻
公开(公告)号：US06653214B1
公开(公告)日：2003-11-25
申请号：US10034747
申请日：2002-01-03
申请人： Tony K. Quach , G. David Via , James S. Sewell , Christopher A. Bozada , Gregory C. DeSalvo , Ross W. Dettmer , John L. Ebel , James K. Gillespie , Thomas Jenkins , Kenichi Nakano
发明人： Tony K. Quach , G. David Via , James S. Sewell , Christopher A. Bozada , Gregory C. DeSalvo , Ross W. Dettmer , John L. Ebel , James K. Gillespie , Thomas Jenkins , Kenichi Nakano
IPC分类号： H01L2144
CPC分类号： H01L21/76898 , H01L23/481 , H01L23/66 , H01L2223/6616 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit substrate via-hole fabrication arrangement providing for accurate determination of via-hole size and via-hole registration through use of a calibrated pattern formed into the integrated circuit substrate during portions of the normal circuit fabrication process. Initiation of the via-hole and fabrication of the calibrated pattern from one surface, such as the front side, of the integrated circuit wafer and completion of the via-hole from the opposite surface of the wafer are contemplated. The calibrated pattern may be one of several possible physical configurations and of selected dimensions usable with the process, materials and circuitry of the device being fabricated. Use of the invention in fabricating ground conductor-connected via conductors for gigahertz radio frequency-capable integrated circuits of the monolithic or mixed hybrid with monolithic type and having a ground plane element is contemplated.
摘要翻译：一种集成电路衬底通孔制造装置，其通过在正常电路制造工艺的部分期间通过使用形成在集成电路衬底中的校准图案来准确地确定通孔尺寸和通孔配准。设想从集成电路晶片的一个表面（例如前侧）开始通孔并制造校准图案，并且从晶片的相对表面完成通孔。校准图案可以是几个可能的物理配置中的一个以及可用于正在制造的设备的工艺，材料和电路的选定尺寸之一。设想将本发明用于制造具有整体式或具有接地平面元件的单片或混合混合物的千兆赫兹无线电频率集成电路的接地导体连接通孔导体。

13. 发明授权

US06884717B1 Stiffened backside fabrication for microwave radio frequency wafers 失效
标题翻译：加强微波射频晶片的背面制造
公开(公告)号：US06884717B1
公开(公告)日：2005-04-26
申请号：US10034723
申请日：2002-01-03
申请人： Gregory C. Desalvo , Tony K. Quach , John L. Ebel , Anders P. Walker , Paul D. Cassity
发明人： Gregory C. Desalvo , Tony K. Quach , John L. Ebel , Anders P. Walker , Paul D. Cassity
IPC分类号： H01L21/306 , H01L21/308 , H01L21/44 , H01L21/768 , H01L21/78 , H01L23/66
CPC分类号： H01L21/78 , H01L21/306 , H01L21/3083 , H01L21/76898 , H01L23/4824 , H01L23/66 , H01L2924/0002 , H01L2924/00
摘要： An etching based semiconductor wafer thinning arrangement usable as an improved alternative to the usual grinding and polishing wafer thinning. The thinned wafer includes a structurally enhancing wafer backside grid array of original wafer thickness semiconductor material with grid cells surrounding individual thinned wafer areas and serving to improve the strength and physical rigidity characteristics of the thinned wafer. Preferably this grid array is supplemented with an additional, wafer periphery-located, backside ring of semiconductor material also of original wafer thickness. Ability to avoid a wafer front side mounting during thinning accomplishment, fast etching, reduced wafer breakage, enhanced wafer strength and improved wafer handling achieved with the disclosed thinning arrangement all contribute to achieved advantages over conventional wafer thinning. Gallium arsenide or other semiconductor materials are contemplated along with use in radio frequency or other integrated circuit devices of either the single transistor or complete integrated circuit components types.
摘要翻译：基于蚀刻的半导体晶片薄化布置可用作通常的研磨和抛光晶片薄化的改进的替代。薄化晶片包括结构上增强的原始晶片厚度半导体材料的晶片背面格栅阵列，其具有围绕各个薄化晶片区域的栅格单元，并且用于提高薄晶片的强度和物理刚度特性。优选地，该栅格阵列补充有另外的晶片周边位于的也是原始晶片厚度的半导体材料的背面环。通过所公开的稀化装置实现的减薄完成，快速蚀刻，减少的晶片断裂，增强的晶片强度以及改进的晶片处理，能够避免晶片正面安装，这都有助于实现优于常规晶片薄化的优点。考虑砷化镓或其他半导体材料，以及在单晶体管或完整集成电路组件类型的射频或其他集成电路器件中的使用。

14. 发明授权

US07381583B1 MEMS RF switch integrated process 有权
标题翻译： MEMS射频开关集成工艺
公开(公告)号：US07381583B1
公开(公告)日：2008-06-03
申请号：US10901315
申请日：2004-07-27
申请人： John L. Ebel , Rebecca Cortez , Richard E. Strawser , Kevin D. Leedy
发明人： John L. Ebel , Rebecca Cortez , Richard E. Strawser , Kevin D. Leedy
IPC分类号： H01L21/00
CPC分类号： B81C1/00333 , B81B2201/018 , B81C2203/0154 , H01H59/0009
摘要： A capacitance coupled, transmission line-fed, radio frequency MEMS switch and its fabrication process using photoresist and other low temperature processing steps are described. The achieved switch is disposed in a low cost dielectric housing free of undesired electrical effects on the switch and on the transmission line(s) coupling the switch to an electrical circuit. The dielectric housing is provided with an array of sealable apertures useful for wet, but hydrofluoric acid-free, removal of switch fabrication employed materials and also useful during processing for controlling the operating atmosphere surrounding the switch—e.g. at a pressure above the high vacuum level for enhanced switch damping during operation. Alternative arrangements for sealing an array of dielectric housing apertures are included. Processing details including plan and profile drawing views, specific equipment and materials identifications, temperatures and times are also disclosed.
摘要翻译：描述了电容耦合，传输线馈电，射频MEMS开关及其使用光致抗蚀剂和其它低温处理步骤的制造工艺。所实现的开关设置在低成本的绝缘壳体中，在开关上以及将开关耦合到电路的传输线上不受不利影响。绝缘壳体设置有可用于湿的但不含氢氟酸的可密封的孔阵列，其除去开关制造所采用的材料，并且在用于控制开关周围的操作气氛的处理期间也是有用的。在高真空水平以上的压力下，用于在运行期间增强开关阻尼。包括用于密封绝缘壳体孔阵列的替代布置。还披露了包括计划和剖面图，特定设备和材料标识，温度和时间在内的处理细节。

15. 发明授权

US07977137B1 Latching zip-mode actuated mono wafer MEMS switch method 有权
标题翻译：闭锁拉链模式致动单晶片MEMS开关方法
公开(公告)号：US07977137B1
公开(公告)日：2011-07-12
申请号：US12152130
申请日：2008-05-08
申请人： John L. Ebel , Rebecca Cortez , Kevin D. Leedy , Richard E. Strawser , Donald E. Strawser, legal representative
发明人： John L. Ebel , Rebecca Cortez , Kevin D. Leedy , Richard E. Strawser
IPC分类号： H01L21/00
CPC分类号： H01H59/0009 , B81B7/0064 , B81B2201/014 , B81B2201/018 , B81B2207/096 , B81C2201/0108 , B81C2203/0136 , B81C2203/0154 , H01H2059/0045
摘要： A process for making a latching zip-mode actuated mono wafer MEMS switch especially suited to capacitance coupled signal switching of microwave radio frequency signals is disclosed. The single wafer fabrication process used for the switch employs sacrificial layers and liquid removal of these layers in order to also provide needed permanent physical protection for an ultra fragile switch moving arm member. Latched operation of the achieved MEMS switch without use of conventional holding electrodes or magnetic fields is also achieved. Fabrication of a single MEMS switch is disclosed however large or small arrays may be achieved. A liquid removal based fabrication process is disclosed.
摘要翻译：公开了一种用于制造特别适用于微波射频信号的电容耦合信号切换的闭锁拉链模式致动单晶片MEMS开关的方法。用于开关的单个晶片制造工艺采用牺牲层和这些层的液体移除，以便为超脆弱的开关移动臂构件提供所需的永久物理保护。还实现了不使用常规保持电极或磁场的实现的MEMS开关的锁定操作。公开了单个MEMS开关的制造，但是可以实现大的或小的阵列。公开了一种基于液体去除的制造方法。

16. 发明授权

US07145213B1 MEMS RF switch integrated process 有权
标题翻译： MEMS射频开关
公开(公告)号：US07145213B1
公开(公告)日：2006-12-05
申请号：US10901314
申请日：2004-07-27
申请人： John L. Ebel , Rebecca Cortez , Richard E. Strawser , Kevin D. Leedy
发明人： John L. Ebel , Rebecca Cortez , Richard E. Strawser , Kevin D. Leedy
IPC分类号： H01L21/14
CPC分类号： H01H59/0009
摘要： A capacitance coupled, transmission line-fed, radio frequency MEMS switch and its fabrication process using photoresist and other low temperature processing steps are described. The achieved switch is disposed in a low cost dielectric housing free of undesired electrical effects on the switch and on the transmission line(s) coupling the switch to an electrical circuit. The dielectric housing is provided with an array of sealable apertures useful for wet, but hydrofluoric acid-free, removal of switch fabrication employed materials and also useful during processing for controlling the operating atmosphere surrounding the switch—e.g. at a pressure above the high vacuum level for enhanced switch damping during operation. Alternative arrangements for sealing an array of dielectric housing apertures are included. Processing details including plan and profile drawing views, specific equipment and materials identifications, temperatures and times are also disclosed.
摘要翻译：描述了一种电容耦合，传输线馈电，射频MEMS开关设备，可利用低温光刻胶基于晶片刻度的加工步骤。开关装置设置在低成本的绝缘壳体中，不会对开关和将开关耦合到电路的传输线路产生不期望的电效应。介电壳体设置有可用于湿式但不含氢氟酸的可密封孔的阵列，其除去开关制造用材料，并且在用于控制开关周围的操作气氛的处理期间也是有用的，例如在高于高压真空度可在运行期间增强和选择开关阻尼。包括介质壳体孔阵列的替代密封装置。包括计划和简档图纸视图，特定设备和材料标识，温度和时间的处理细节。 MEMS开关也可以是金属接触型。

17. 发明授权

US07960804B1 Latching zip-mode actuated mono wafer MEMS switch 有权
标题翻译：锁定拉链模式致动单晶片MEMS开关
公开(公告)号：US07960804B1
公开(公告)日：2011-06-14
申请号：US12152129
申请日：2008-05-08
申请人： John L. Ebel , Rebecca Cortez , Kevin D. Leedy , Richard E. Strawser , Donald E. Strawser, legal representative
发明人： John L. Ebel , Rebecca Cortez , Kevin D. Leedy , Richard E. Strawser
IPC分类号： H01L21/00
CPC分类号： H01H59/0009 , B81B2201/018 , B81C1/00333 , B81C2203/0154 , H01H2059/0045
摘要： A latching zip-mode actuated mono wafer MEMS switch especially suited to capacitance coupled signal switching of microwave radio frequency signals is disclosed. The single wafer fabrication process used for the switch employs sacrificial layers and liquid removal of these layers in order to also provide needed permanent physical protection for an ultra fragile switch moving arm member. Latched operation of the achieved MEMS switch without use of conventional holding electrodes or magnetic fields is also achieved. Fabrication of a single MEMS switch is disclosed however large or small arrays may be achieved.
摘要翻译：公开了一种特别适用于微波射频信号的电容耦合信号切换的闭锁拉链模式致动单晶片MEMS开关。用于开关的单个晶片制造工艺采用牺牲层和这些层的液体移除，以便为超脆弱的开关移动臂构件提供所需的永久物理保护。还实现了不使用常规保持电极或磁场的实现的MEMS开关的锁定操作。公开了单个MEMS开关的制造，但是可以实现大的或小的阵列。

18. 发明授权

US07617577B2 Method of forming a low cost digital variable capacitor 失效
标题翻译：形成低成本数字可变电容器的方法
公开(公告)号：US07617577B2
公开(公告)日：2009-11-17
申请号：US11216261
申请日：2005-08-31
申请人： John L. Ebel , Rebecca Cortez , Richard E. Strawser , Kevin D. Leedy
发明人： John L. Ebel , Rebecca Cortez , Richard E. Strawser , Kevin D. Leedy
IPC分类号： H01G7/00
CPC分类号： H01G5/18 , G11C11/565 , H01L28/60 , Y10T29/417 , Y10T29/42 , Y10T29/435 , Y10T29/49005 , Y10T29/4908
摘要： A digital variable capacitor package is provided as having a ground plane disposed on predetermined portion of the top surface of a substrate. An elongated signal electrode may also be disposed on the substrate and including a first end defining an input and a second end extending to a substantially central region of the top surface of the substrate. This elongated signal electrode is disposed to be electrically isolated from the ground plane. A number of elongated cantilevers are disposed on the substrate and each include first ends coupled to the second end of the signal electrode and each further include second ends suspended over different predetermined portions of the ground plane. In operation, one or more of the cantilevers may be actuated to move portion thereof into close proximity to the ground plane for providing one or more discrete capacitance values.
摘要翻译：提供数字可变电容器封装，其具有设置在基板的顶表面的预定部分上的接地平面。细长的信号电极也可以设置在衬底上，并且包括限定输入的第一端和延伸到衬底的顶表面的大致中心区域的第二端。该细长信号电极设置成与接地平面电隔离。许多细长的悬臂设置在基板上，并且每个包括耦合到信号电极的第二端的第一端，并且每个还包括悬挂在接地平面的不同预定部分上的第二端。在操作中，可以致动一个或多个悬臂以将其部分移动到靠近接地平面以提供一个或多个离散电容值。

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