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12. 发明授权

US06445212B1 High-speed, low-noise, impedance-matched output buffer circuit 有权
标题翻译：高速，低噪声，阻抗匹配的输出缓冲电路
公开(公告)号：US06445212B1
公开(公告)日：2002-09-03
申请号：US09829231
申请日：2001-04-09
申请人： Meng-Jer Wey , Chu Yu Chin
发明人： Meng-Jer Wey , Chu Yu Chin
IPC分类号： H03K190175
CPC分类号： H03K17/164
摘要： A programmable multi-configuration output buffer circuit having an input port terminal and an output port terminal. The output buffer circuit includes an output buffer stage having no delay unit and one or more output buffer stages having a delay unit. The output buffer stage having no delay unit includes a first type channel pull up transistor, a second type channel pull down transistor and a first logic circuit. The drain terminal of the first type channel pull up transistor and the second type channel pull down transistor are connected together and connected with the output port as well. The first logic circuit receives an enable signal and an input signal. The output buffer stage having a delay unit therein includes a first type channel pull up transistor, a second type channel pull down transistor and a second logic circuit. The drain terminal of the first type channel pull up transistor and the second type channel pull down transistor are connected together and connects with the output port as well. The second logic circuit is connected to the enable signal, the input signal and a corresponding select enable signal. The output buffer circuit may further includes a programmable storage unit for controlling output configuration. When the output buffer circuit is programmed, select enable signals can be outputted so that a portion of the output buffer stages having a delay unit can be triggered.
摘要翻译：一种具有输入端口和输出端口的可编程多配置输出缓冲电路。输出缓冲器电路包括没有延迟单元的输出缓冲器级和具有延迟单元的一个或多个输出缓冲级。没有延迟单元的输出缓冲级包括第一类型的沟道上拉晶体管，第二类型的沟道下拉晶体管和第一逻辑电路。第一类型沟道上拉晶体管的漏极端子和第二类型沟道下拉晶体管连接在一起并与输出端口连接。第一逻辑电路接收使能信号和输入信号。其中具有延迟单元的输出缓冲级包括第一类型的沟道上拉晶体管，第二类型的沟道下拉晶体管和第二逻辑电路。第一类型沟道上拉晶体管的漏极端子和第二类型沟道下拉晶体管连接在一起并与输出端口连接。第二逻辑电路连接到使能信号，输入信号和相应的选通使能信号。输出缓冲器电路还可以包括用于控制输出配置的可编程存储单元。当输出缓冲器电路被编程时，可以输出选择使能信号，使得可以触发具有延迟单元的输出缓冲级的一部分。

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