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11. 发明申请

US20090263969A1 HIDDEN PLATING TRACES 有权
标题翻译：隐藏的镀层
公开(公告)号：US20090263969A1
公开(公告)日：2009-10-22
申请号：US12493582
申请日：2009-06-29
申请人： Hem Takiar , Cheemen Yu , Ken Jian Ming Wang , Chin-Tien Chiu , Han-Shiao Chen , Chih-Chin Liao
发明人： Hem Takiar , Cheemen Yu , Ken Jian Ming Wang , Chin-Tien Chiu , Han-Shiao Chen , Chih-Chin Liao
IPC分类号： H01L21/3205
CPC分类号： H01L25/0657 , H01L21/3205 , H01L23/04 , H01L23/3121 , H01L23/5386 , H01L24/48 , H01L24/64 , H01L24/65 , H01L2224/32145 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/10253 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.
摘要翻译：公开了一种加强的半导体管芯基板和封装。衬底可以包括形成有非线性边缘的接触指状物。向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。

12. 发明申请

US20090065902A1 METHOD OF FORMING A SEMICONDUCTOR DIE HAVING A SLOPED EDGE FOR RECEIVING AN ELECTRICAL CONNECTOR 审中-公开
标题翻译：形成用于接收电连接器的斜坡边缘的半导体器件的方法
公开(公告)号：US20090065902A1
公开(公告)日：2009-03-12
申请号：US11853428
申请日：2007-09-11
申请人： Cheemen Yu , Chih-Chin Liao , Hem Takiar
发明人： Cheemen Yu , Chih-Chin Liao , Hem Takiar
IPC分类号： H01L29/06 , H01L21/304 , H01L21/56
CPC分类号： H01L21/3043 , H01L21/78 , H01L23/3121 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/05554 , H01L2224/24011 , H01L2224/24051 , H01L2224/24145 , H01L2224/24226 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/76155 , H01L2224/82102 , H01L2224/97 , H01L2225/06551 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/351 , H01L2924/00014 , H01L2224/82 , H01L2924/00 , H01L2924/00012
摘要： A method of forming a low profile semiconductor package, and a semiconductor package formed thereby, is disclosed. The semiconductor die is formed with one or more sloped edges on which electrically conductive traces may be deposited to allow the semiconductor die to be coupled to another die and/or a substrate on which the die is mounted. Depositing the electrical traces directly on the surface and sloped edge of the die allows the die to be electrically coupled without bond wires, thereby allowing a reduction in the overall thickness of the package.
摘要翻译：公开了一种形成低轮廓半导体封装的方法，以及由此形成的半导体封装。半导体管芯形成有一个或多个倾斜边缘，导电迹线可以沉积在其上，以允许半导体管芯耦合到另一管芯和/或其上安装管芯的衬底。将电迹线直接沉积在模具的表面和倾斜边缘上，使得模具能够电耦合而没有接合线，从而允许减小包装的整体厚度。

13. 发明申请

US20070267759A1 Semiconductor device with a distributed plating pattern 审中-公开
标题翻译：具有分布电镀图案的半导体器件
公开(公告)号：US20070267759A1
公开(公告)日：2007-11-22
申请号：US11435518
申请日：2006-05-17
申请人： Chih-Chin Liao , Han-Shiao Chen , Chin-Tien Chiu , Cheemen Yu , Hem Takiar
发明人： Chih-Chin Liao , Han-Shiao Chen , Chin-Tien Chiu , Cheemen Yu , Hem Takiar
IPC分类号： H01L23/48
CPC分类号： H05K3/243 , H01L23/49838 , H01L2924/0002 , H05K1/0271 , H05K3/28 , H05K2201/09781 , H05K2201/0989 , H01L2924/00
摘要： A substrate, and a semiconductor die package formed therefrom, are disclosed which include a distributed plating pattern for reducing mechanical stress on the semiconductor die. The substrate according to embodiments of the invention may include traces and contact pads plated in a double image plating process. Additionally, the substrate may include dummy plating areas including plating material. The plated vias and/or traces and the plating material within the dummy plating areas provide a plating pattern which is evenly distributed across the surface of the substrate. The even distribution of the plating pattern prevents peaks and valleys in the finished substrate.
摘要翻译：公开了一种基板和由其形成的半导体管芯封装，其包括用于减小半导体管芯上的机械应力的分布电镀图案。根据本发明的实施例的衬底可以包括以双映像电镀工艺电镀的迹线和接触焊盘。此外，基板可以包括包括电镀材料的虚拟电镀区域。电镀通孔和/或迹线以及虚拟电镀区域内的电镀材料提供均匀分布在基板表面上的电镀图案。电镀图案的均匀分布防止成品基板中的峰和谷。

14. 发明授权

US07772107B2 Methods of forming a single layer substrate for high capacity memory cards 有权
标题翻译：形成高容量存储卡的单层基板的方法
公开(公告)号：US07772107B2
公开(公告)日：2010-08-10
申请号：US11538220
申请日：2006-10-03
申请人： Cheemen Yu , Hem Takiar , Chih-Chin Liao
发明人： Cheemen Yu , Hem Takiar , Chih-Chin Liao
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L21/4846 , H01L21/486 , H01L23/49827 , H01L2224/48091 , H01L2924/01078 , H01L2924/01079 , H01L2924/00014
摘要： Methods of forming a semiconductor package including a single-sided substrate are disclosed. In a first embodiment of the present invention, a substrate may include a conductive layer on a top surface of the substrate, i.e., on the same side of the substrate as where the die are mounted. In a second embodiment of the present invention, a substrate may include a conductive layer on a bottom of the substrate, i.e., on the opposite side of the substrate as where the die are mounted.
摘要翻译：公开了形成包括单面基板的半导体封装的方法。在本发明的第一实施例中，衬底可以在衬底的顶表面上，即在衬底的与安装裸片相同的一侧上包括导电层。在本发明的第二实施例中，衬底可以包括在衬底的底部上的导电层，即衬底的安装模具的相反侧。

15. 发明申请

US20070269929A1 Method of reducing stress on a semiconductor die with a distributed plating pattern 审中-公开
标题翻译：以分布电镀图案减少半导体晶片上的应力的方法
公开(公告)号：US20070269929A1
公开(公告)日：2007-11-22
申请号：US11435954
申请日：2006-05-17
申请人： Chih-Chin Liao , Han-Shiao Chen , Chin-Tien Chiu , Cheemen Yu , Hem Takiar
发明人： Chih-Chin Liao , Han-Shiao Chen , Chin-Tien Chiu , Cheemen Yu , Hem Takiar
IPC分类号： H01L21/00 , H01L21/31
CPC分类号： H01L23/49838 , H01L2924/0002 , H05K1/0271 , H05K3/243 , H05K3/28 , H05K2201/09781 , H01L2924/00
摘要： A substrate, and a semiconductor die package formed therefrom, are disclosed which include a distributed plating pattern for reducing mechanical stress on the semiconductor die. The substrate according to embodiments of the invention may include traces and contact pads plated in a double image plating process. Additionally, the substrate may include dummy plating areas including plating material. The plated vias and/or traces and the plating material within the dummy plating areas provide a plating pattern which is evenly distributed across the surface of the substrate. The even distribution of the plating pattern prevents peaks and valleys in the finished substrate.
摘要翻译：公开了一种基板和由其形成的半导体管芯封装，其包括用于减小半导体管芯上的机械应力的分布电镀图案。根据本发明的实施例的衬底可以包括以双映像电镀工艺电镀的迹线和接触焊盘。此外，基板可以包括包括电镀材料的虚拟电镀区域。电镀通孔和/或迹线以及虚拟电镀区域内的电镀材料提供均匀分布在基板表面上的电镀图案。电镀图案的均匀分布防止成品基板中的峰和谷。

16. 发明授权

US08487441B2 Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging 有权
标题翻译：芯片载体基板上的刚性波纹图案设计和半导体和电子子系统封装的印刷电路板
公开(公告)号：US08487441B2
公开(公告)日：2013-07-16
申请号：US11930816
申请日：2007-10-31
申请人： Chin-Tien Chiu , Chih-Chin Liao , Ken Jian Ming Wang , Han-Shiao Chen , Cheemen Yu , Hem Takiar
发明人： Chin-Tien Chiu , Chih-Chin Liao , Ken Jian Ming Wang , Han-Shiao Chen , Cheemen Yu , Hem Takiar
IPC分类号： H01L23/48 , H01R9/00 , H05K1/11
CPC分类号： H01L23/562 , H01L21/56 , H01L23/3114 , H01L23/3121 , H01L23/48 , H01L23/49805 , H01L23/49822 , H01L23/49838 , H01L23/528 , H01L24/05 , H01L24/06 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/73 , H01L2224/05015 , H01L2224/05023 , H01L2224/0605 , H01L2224/06151 , H01L2224/32057 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83385 , H01L2924/00014 , H01L2924/01004 , H01L2924/0102 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/1438 , H01L2924/15313 , H01L2924/15323 , H01L2924/15333 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.
摘要翻译：形成在半导体管芯封装中的衬底的第一侧上的刚性波形图案。刚性波形图案与形成在基板的第二侧上的接触指状物对准并覆盖在其上。刚性波形包括具有蚀刻部分的第一图案和围绕蚀刻部分的未蚀刻部分。当模制过程中衬底和裸片被封装时，刚性波形有效地减少了模具的变形和应力，从而大大减轻了模具开裂。

17. 发明授权

US08470640B2 Method of fabricating stacked semiconductor package with localized cavities for wire bonding 有权
标题翻译：用于引线接合的具有局部空腔的堆叠半导体封装的方法
公开(公告)号：US08470640B2
公开(公告)日：2013-06-25
申请号：US12165297
申请日：2008-06-30
申请人： Hem Takiar , Shrikar Bhagath , Cheemen Yu , Chih-Chin Liao
发明人： Hem Takiar , Shrikar Bhagath , Cheemen Yu , Chih-Chin Liao
IPC分类号： H01L21/00
CPC分类号： H01L24/85 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L2224/05553 , H01L2224/32506 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48227 , H01L2224/49174 , H01L2224/83801 , H01L2224/85 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/04953 , H01L2924/078 , H01L2924/10155 , H01L2924/10158 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2224/78 , H01L2924/3512 , H01L2924/00
摘要： A method of fabricating a semiconductor die and a low profile semiconductor package are disclosed. The semiconductor package may include at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with localized cavities through a bottom surface of the semiconductor die, along a side edge of the semiconductor die. The one or more localized cavities in a side take up less than the entire side. Thus, the localized cavities allow low height stacking of semiconductor die while providing each die with a high degree of structural integrity to prevent cracking or breaking of the die edge during fabrication.
摘要翻译：公开了半导体管芯和低剖面半导体封装的制造方法。半导体封装可以包括安装到衬底的至少第一和第二堆叠半导体管芯。第一和/或第二半导体管芯可以沿着半导体管芯的侧边缘通过半导体管芯的底表面被制造成具有局部空腔。一个侧面中的一个或多个局部空腔占据整个侧面。因此，局部空腔允许半导体芯片的低高度堆叠，同时为每个模具提供高度的结构完整性，以防止在制造期间模头边缘的破裂或断裂。

18. 发明申请

US20100102440A1 HIGH DENSITY THREE DIMENSIONAL SEMICONDUCTOR DIE PACKAGE 有权
标题翻译：高密度三维半导体封装
公开(公告)号：US20100102440A1
公开(公告)日：2010-04-29
申请号：US12648697
申请日：2009-12-29
申请人： Cheemen Yu , Chih-Chin Liao , Hem Takiar
发明人： Cheemen Yu , Chih-Chin Liao , Hem Takiar
IPC分类号： H01L25/16 , H01L23/04
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/04 , G11C5/143 , G11C8/12 , H01L21/485 , H01L23/5382 , H01L25/50 , H01L2225/06527 , H01L2225/06579 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates. By providing each flash memory semiconductor die on a substrate with a unique layout of address traces, each memory die may be selectively addressed by the controller die.
摘要翻译：公开了一种半导体封装，其包括安装在基板的堆叠和接合层上的多个半导体管芯，例如在带自动焊接工艺中使用的聚酰亚胺带。带可以具有多个重复图案的迹线和形成在其上的接触垫。每个迹线包括在衬底的相应顶部和底部表面上的对准的互连焊盘，用于在将图案从基板切割成对准和堆叠之后将一个图案的迹线粘合到另一图案的迹线。诸如闪速存储器和控制器管芯的半导体管芯安装在衬底上各个图案的迹线上。为了使控制器裸片独特地寻址堆叠中的特定闪存芯片，支持存储芯片的每个衬底上的一组迹线被用作地址引脚，并相对于其它衬底的迹线的布局以独特的布局冲压。通过在基板上提供具有唯一的地址迹线布局的每个闪速存储器半导体管芯，每个存储管芯可以被控制器管芯选择性地寻址。

19. 发明申请

US20080182365A1 DIE PACKAGE WITH ASYMMETRIC LEADFRAME CONNECTION 有权
标题翻译： DIY包装与不对称铅笔连接
公开(公告)号：US20080182365A1
公开(公告)日：2008-07-31
申请号：US12060418
申请日：2008-04-01
申请人： Ming Hsun Lee , Chih-Chin Liao , Cheemen Yu , Hem Takiar
发明人： Ming Hsun Lee , Chih-Chin Liao , Cheemen Yu , Hem Takiar
IPC分类号： H01L21/60
CPC分类号： H01L23/4951 , H01L23/49551 , H01L23/49558 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05553 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/49109 , H01L2224/73265 , H01L2225/06562 , H01L2924/00014 , H01L2924/01087 , H01L2924/10161 , H01L2924/14 , H01L2924/181 , H01L2924/18165 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A leadframe for a semiconductor package is disclosed including electrical leads which extend from one side of the leadframe to an opposite side of the leadframe, where electrical connection may be made with the semiconductor die at the second side of the leadframe. The semiconductor die may be supported on the leads extending across the leadframe. The package may further include a spacer layer affixed to the electrical leads to fortify the semiconductor package and to prevent exposure of the electrical leads during the molding of the package.
摘要翻译：公开了一种用于半导体封装的引线框架，其包括从引线框架的一侧延伸到引线框架的相反侧的电引线，其中可以在引线框架的第二侧与半导体管芯进行电连接。半导体管芯可以被支撑在引导框架上延伸的引线上。封装还可以包括固定到电引线上的间隔层，以强化半导体封装并防止在封装成型期间电引线的暴露。

20. 发明授权

US07355283B2 Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging 有权
标题翻译：芯片载体基板上的刚性波纹图案设计和半导体和电子子系统封装的印刷电路板
公开(公告)号：US07355283B2
公开(公告)日：2008-04-08
申请号：US11106699
申请日：2005-04-14
申请人： Chin-Tien Chiu , Chih-Chin Liao , Ken Jian Ming Wang , Han-Shiao Chen , Cheemen Yu , Hem Takiar
发明人： Chin-Tien Chiu , Chih-Chin Liao , Ken Jian Ming Wang , Han-Shiao Chen , Cheemen Yu , Hem Takiar
IPC分类号： H01L23/48 , H01R9/00 , H05K1/11
CPC分类号： H01L23/562 , H01L21/56 , H01L23/3114 , H01L23/3121 , H01L23/48 , H01L23/49805 , H01L23/49822 , H01L23/49838 , H01L23/528 , H01L24/05 , H01L24/06 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/73 , H01L2224/05015 , H01L2224/05023 , H01L2224/0605 , H01L2224/06151 , H01L2224/32057 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83385 , H01L2924/00014 , H01L2924/01004 , H01L2924/0102 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/1438 , H01L2924/15313 , H01L2924/15323 , H01L2924/15333 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.
摘要翻译：形成在半导体管芯封装中的衬底的第一侧上的刚性波形图案。刚性波形图案与形成在基板的第二侧上的接触指状物对准并覆盖在其上。当模制过程中衬底和裸片被封装时，刚性波形有效地减少了模具的变形和应力，从而大大减轻了模具开裂。

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