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11. 发明申请

US20110147853A1 Method of Forming an Electrical Fuse and a Metal Gate Transistor and the Related Electrical Fuse 有权
标题翻译：形成电保险丝和金属栅晶体管的方法及相关电熔丝
公开(公告)号：US20110147853A1
公开(公告)日：2011-06-23
申请号：US12641322
申请日：2009-12-18
申请人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
发明人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
IPC分类号： H01L27/06 , H01L21/768 , H01L21/8234 , H01L23/525
CPC分类号： H01L23/5256 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L27/112 , H01L27/11206 , H01L29/7843 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.
摘要翻译：本发明提供了一种将电熔丝工艺集成到高k /金属栅极工艺中的方法。该方法同时形成晶体管的虚拟栅极堆叠和电子熔丝的虚拟栅极堆叠; 并且同时去除晶体管区域中的虚拟栅极堆叠的多晶硅和电子熔丝区域中的伪栅极堆叠的多晶硅。此后，去除设置在电熔丝区域的开口中的功函数金属层; 并且晶体管区域中的开口和具有金属导电结构的e熔丝区域中的开口被填充以形成晶体管的电熔丝和金属栅极。

12. 发明授权

US08399318B2 Method of forming an electrical fuse and a metal gate transistor and the related electrical fuse 有权
标题翻译：形成电熔丝和金属栅晶体管及相关电熔丝的方法
公开(公告)号：US08399318B2
公开(公告)日：2013-03-19
申请号：US13469069
申请日：2012-05-10
申请人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
发明人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
IPC分类号： H01L21/8238
CPC分类号： H01L23/5256 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L27/112 , H01L27/11206 , H01L29/7843 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.
摘要翻译：本发明提供了一种将电熔丝工艺集成到高k /金属栅极工艺中的方法。该方法同时形成晶体管的虚拟栅极堆叠和电子熔丝的虚拟栅极堆叠; 并且同时去除晶体管区域中的虚拟栅极堆叠的多晶硅和电子熔丝区域中的伪栅极堆叠的多晶硅。此后，去除设置在电熔丝区域的开口中的功函数金属层; 并且晶体管区域中的开口和具有金属导电结构的e熔丝区域中的开口被填充以形成晶体管的电熔丝和金属栅极。

13. 发明授权

US08035191B2 Contact efuse structure 有权
标题翻译：联系efuse结构
公开(公告)号：US08035191B2
公开(公告)日：2011-10-11
申请号：US12326106
申请日：2008-12-02
申请人： Yung-Chang Lin , Kuei-Sheng Wu , San-Fu Lin , Hui-Shen Shih
发明人： Yung-Chang Lin , Kuei-Sheng Wu , San-Fu Lin , Hui-Shen Shih
IPC分类号： H01L29/00
CPC分类号： H01L27/112 , H01L23/5256 , H01L27/11206 , H01L29/665 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A contact efuse structure includes a silicon layer and a contact contacting the silicon layer with one end. When a voltage is applied to the contact, a void is formed at the end of the contact, and thus the contact is open. Such structure may be utilized in an efuse device or a read only memory. A method of making a contact efuse device and a method of making a read only memory are also disclosed.
摘要翻译：接触式熔点结构包括硅层和接触硅层与一端的接触。当对触点施加电压时，在接触端部形成空隙，因此触点断开。这种结构可以用在efuse设备或只读存储器中。还公开了制造接触式充电装置的方法和制造只读存储器的方法。

14. 发明申请

US20100133649A1 Contact efuse structure, method of making a contact efuse device containing the same, and method of making a read only memory containing the same 有权
标题翻译：联系efuse结构，制造包含该接触式efuse器件的接触式设备的方法以及制造只读存储器的方法
公开(公告)号：US20100133649A1
公开(公告)日：2010-06-03
申请号：US12326106
申请日：2008-12-02
申请人： Yung-Chang Lin , Kuei-Sheng Wu , San-Fu Lin , Hui-Shen Shih
发明人： Yung-Chang Lin , Kuei-Sheng Wu , San-Fu Lin , Hui-Shen Shih
IPC分类号： H01L29/66 , H01L21/44 , H01L21/336
CPC分类号： H01L27/112 , H01L23/5256 , H01L27/11206 , H01L29/665 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A contact efuse structure includes a silicon layer and a contact contacting the silicon layer with one end. When a voltage is applied to the contact, a void is formed at the end of the contact, and thus the contact is open. Such structure may be utilized in an efuse device or a read only memory. A method of making a contact efuse device and a method of making a read only memory are also disclosed.
摘要翻译：接触式熔点结构包括硅层和接触硅层与一端的接触。当对触点施加电压时，在接触端部形成空隙，因此触点断开。这种结构可以用在efuse设备或只读存储器中。还公开了制造接触式充电装置的方法和制造只读存储器的方法。

15. 发明申请

US20120225524A1 METHOD OF FORMING AN ELECTRICAL FUSE AND A METAL GATE TRANSISTOR AND THE RELATED ELECTRICAL FUSE 有权
公开(公告)号：US20120225524A1
公开(公告)日：2012-09-06
申请号：US13469069
申请日：2012-05-10
申请人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
发明人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
IPC分类号： H01L21/8232
CPC分类号： H01L23/5256 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L27/112 , H01L27/11206 , H01L29/7843 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.

16. 发明申请

US20110117710A1 METHOD OF FABRICATING EFUSE, RESISTOR AND TRANSISTOR 有权
标题翻译：制造EFUSE，电阻和晶体管的方法
公开(公告)号：US20110117710A1
公开(公告)日：2011-05-19
申请号：US12621518
申请日：2009-11-19
申请人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong , Ching-Hsiang Tseng
发明人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong , Ching-Hsiang Tseng
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823842 , H01L27/0629 , H01L29/7848
摘要： A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric layer, a polysilicon layer and a hard mask. Later, a source/drain doping region is formed in the substrate besides the gate. After that, the hard mask in the resistor and the efuse is removed. Subsequently, a salicide process is performed to form a silicide layer on the source/drain doping region, the resistor, and the efuse. Then, a planarized second dielectric layer is formed on the substrate and the polysilicon in the gate is exposed. Later, the polysilicon in the gate is removed to form a recess. Finally a metal layer is formed to fill up the recess.
摘要翻译：一种制造efuse，电阻器和晶体管的方法包括以下步骤：提供衬底。然后，在衬底上形成栅极，电阻器和efuse，其中栅极，电阻器和efuse一起包括第一介电层，多晶硅层和硬掩模。之后，在栅极之外的基板中形成源极/漏极掺杂区域。之后，去除电阻和efuse中的硬掩模。随后，执行自对准硅化处理以在源/漏掺杂区域，电阻器和efuse上形成硅化物层。然后，在基板上形成平坦化的第二介质层，露出栅极中的多晶硅。之后，去除栅极中的多晶硅以形成凹陷。最后，形成一个金属层以填充凹槽。

17. 发明申请

US20070238244A1 TRENCH-CAPACITOR DRAM DEVICE AND MANUFACTURE METHOD THEREOF 有权
标题翻译： TRENCH-CAPACITOR DRAM器件及其制造方法
公开(公告)号：US20070238244A1
公开(公告)日：2007-10-11
申请号：US11279254
申请日：2006-04-11
申请人： Yung-Chang Lin , Sun-Chieh Chien , Chien-Li Kuo , Ruey-Chyr Lee
发明人： Yung-Chang Lin , Sun-Chieh Chien , Chien-Li Kuo , Ruey-Chyr Lee
IPC分类号： H01L21/8242 , H01L21/336 , H01L29/94 , H01L21/20
CPC分类号： H01L29/945 , H01L27/1087 , H01L29/66181
摘要： A trench capacitor structure includes a semiconductor substrate comprising thereon a STI structure. A capacitor deep trench is etched into the semiconductor substrate. Collar oxide layer is disposed on inner surface of the capacitor deep trench. A first doped polysilicon layer is disposed on the collar oxide layer and on the exposed bottom of the capacitor deep trench. A capacitor dielectric layer is formed on the first doped polysilicon layer. A second doped polysilicon layer is formed on the capacitor dielectric layer. A deep ion well is formed in the semiconductor substrate, wherein the deep ion well is electrically connected with the first doped polysilicon layer through the bottom of the capacitor deep trench. A passing gate insulation (PGI) layer is formed on the second doped polysilicon layer and on the STI structure.
摘要翻译：沟槽电容器结构包括其上包括STI结构的半导体衬底。电容器深沟槽被蚀刻到半导体衬底中。环状氧化物层设置在电容器深沟槽的内表面上。第一掺杂多晶硅层设置在轴环氧化物层和电容器深沟槽的暴露的底部上。在第一掺杂多晶硅层上形成电容器电介质层。第二掺杂多晶硅层形成在电容器介电层上。在半导体衬底中形成深离子阱，其中深离子阱通过电容器深沟槽的底部与第一掺杂多晶硅层电连接。在第二掺杂多晶硅层和STI结构上形成通过栅极绝缘（PGI）层。

18. 发明授权

US09275933B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09275933B2
公开(公告)日：2016-03-01
申请号：US13526533
申请日：2012-06-19
申请人： Chien-Li Kuo , Yung-Chang Lin
发明人： Chien-Li Kuo , Yung-Chang Lin
IPC分类号： H01L29/49 , H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/76802 , H01L21/76843 , H01L21/76877 , H01L21/823475 , H01L23/481 , H01L29/0649 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination.
摘要翻译：半导体器件包括衬底; 设置在所述基板上的层间电介质; 穿透底物和ILD的TSV。此外，在衬底中设置多个浅沟槽隔离（STI），并且屏蔽环设置在围绕STI上的TSV的ILD中。在形成TSV的过程中，接触环可以保护邻近部件免受金属污染。

19. 发明申请

US20130334699A1 SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130334699A1
公开(公告)日：2013-12-19
申请号：US13526546
申请日：2012-06-19
申请人： Chien-Li Kuo , Yung-Chang Lin
发明人： Chien-Li Kuo , Yung-Chang Lin
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/0228 , H01L21/02282 , H01L21/28026 , H01L21/31111 , H01L21/76224 , H01L21/76802 , H01L21/76831 , H01L21/76843 , H01L21/76877 , H01L2224/05009 , H01L2224/0557 , H01L2224/06181
摘要： A semiconductor device includes a substrate with a front side and a back side, an ILD, disposed on the substrate, a cap layer disposed on the backside of the substrate, a TSV penetrating the cap layer, the substrate and the ILD, wherein a cap layer sidewall in the TSV juts out beyond the substrate sidewall the TSV with a predetermined distance, and a liner is disposed on the substrate sidewall, wherein the liner partially overlaps with the cap layer.
摘要翻译：一种半导体器件包括具有正面和背面的衬底，设置在衬底上的ILD，设置在衬底背面上的覆盖层，穿透覆盖层，衬底和ILD的TSV，其中帽 TSV中的层侧壁突出超过基板侧壁具有预定距离的TSV，并且衬垫设置在衬底侧壁上，其中衬垫部分地与盖层重叠。

20. 发明申请

US20130334669A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130334669A1
公开(公告)日：2013-12-19
申请号：US13526533
申请日：2012-06-19
申请人： Chien-Li Kuo , Yung-Chang Lin
发明人： Chien-Li Kuo , Yung-Chang Lin
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/76802 , H01L21/76843 , H01L21/76877 , H01L21/823475 , H01L23/481 , H01L29/0649 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination.
摘要翻译：半导体器件包括衬底; 设置在所述基板上的层间电介质; 穿透底物和ILD的TSV。此外，在衬底中设置多个浅沟槽隔离（STI），并且屏蔽环设置在围绕STI上的TSV的ILD中。在形成TSV的过程中，接触环可以保护邻近部件免受金属污染。

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