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11. 发明申请

US20080227288A1 Dual damascene process 有权
标题翻译：双镶嵌工艺
公开(公告)号：US20080227288A1
公开(公告)日：2008-09-18
申请号：US11724284
申请日：2007-03-15
申请人： Po-Zen Chen , Tzu-Chan Weng , Chien-Chung Chen
发明人： Po-Zen Chen , Tzu-Chan Weng , Chien-Chung Chen
IPC分类号： H01L21/4763 , H01L21/311
CPC分类号： H01L21/31144 , H01L21/02063 , H01L21/31138 , H01L21/76811
摘要： A dual damascene process. A first photoresist layer with a first opening corresponding to a trench pattern is formed on a dielectric layer. A second photoresist layer with a second opening corresponding to a via pattern smaller then the trench pattern is formed on the first photoresist layer and extends to a portion of the dielectric layer. The second photoresist layer has a material character different from the first photoresist layer. A via etching process using the second photoresist as a mask is performed to form a via hole passing through the dielectric layer. A photoresist ashing process is performed to remove the second photoresist layer. A trench etching process using the first photoresist layer as a mask is performed to form a trench in the upper portion of the dielectric layer. The via etching process, the photoresist ashing process and the trench etching process are performed as a continuous process in one chamber.
摘要翻译：双镶嵌工艺。在电介质层上形成具有对应于沟槽图案的第一开口的第一光致抗蚀剂层。在第一光致抗蚀剂层上形成具有对应于小于沟槽图案的通孔图案的第二开口的第二光致抗蚀剂层并且延伸到介电层的一部分。第二光致抗蚀剂层具有与第一光致抗蚀剂层不同的材料特性。执行使用第二光致抗蚀剂作为掩模的通孔蚀刻工艺，以形成穿过介电层的通孔。进行光致抗蚀剂灰化处理以去除第二光致抗蚀剂层。执行使用第一光致抗蚀剂层作为掩模的沟槽蚀刻工艺，以在电介质层的上部形成沟槽。通孔蚀刻工艺，光致抗蚀剂灰化处理和沟槽蚀刻工艺在一个室中作为连续工艺进行。

12. 发明申请

US20060241802A1 REAL-TIME MANAGEMENT SYSTEMS AND METHODS FOR MANUFACTURING MANAGEMENT AND YIELD RATE ANALYSIS INTEGRATION 失效
标题翻译：实时管理系统及其制造管理和收费率分析整合方法
公开(公告)号：US20060241802A1
公开(公告)日：2006-10-26
申请号：US11228361
申请日：2005-09-19
申请人： Chien-Chung Chen , Sheng-Jen Wang , Yu-Wen Ho
发明人： Chien-Chung Chen , Sheng-Jen Wang , Yu-Wen Ho
IPC分类号： G06F19/00
CPC分类号： H01L21/67276 , G05B15/02 , G05B23/024 , G05B2219/1112 , G05B2219/45031 , G05B2223/02
摘要： A real-time management method for manufacturing management and yield rate analysis integration. A plurality of yield rates relating to wafer products are summed and averaged for a historical yield rate. Multiple representational inline QC parameters are selected. A statistical process is implemented and, if no extreme value and collinear parameter exists and if analysis results satisfy normal distribution, multiple optimum inline QC parameters are selected from the representational inline QC parameters. Weights of each optimum inline QC parameter are calculated. A predicted yield rate is calculated according to the historical yield rate, weights, and a plurality of measurement and target values relating to the wafer products.
摘要翻译：制造管理和产出率分析整合的实时管理方法。将与晶片产品相关的多个屈服率以历史产量率相加和平均。选择多个代表性的在线QC参数。实施统计过程，如果没有极值和共线参数存在，并且如果分析结果满足正态分布，则从表示的在线QC参数中选择多个最佳在线QC参数。计算每个最佳在线QC参数的权值。根据历史收益率，权重以及与晶片产品相关的多个测量值和目标值来计算预测收益率。

13. 发明授权

US06961013B2 Guaranteed monotonic digital to analog converter 有权
公开(公告)号：US06961013B2
公开(公告)日：2005-11-01
申请号：US10916728
申请日：2004-08-12
申请人： Heng-Chih Lin , Chien-Chung Chen , Solti Peng
发明人： Heng-Chih Lin , Chien-Chung Chen , Solti Peng
IPC分类号： H03M1/06 , H03M1/12 , H03M1/66 , H03M1/68
CPC分类号： H03M1/0641 , H03M1/687
摘要： A hybrid Nyquist thermometer and sigma delta digital to analog converter is presented. The digital input signal is divided into most significant bits and least significant bits. The most significant bits are converted to a thermometer code. A thermometer element array is controlled by the thermometer code. A fractional value is calculated from the least significant bits and used to dither the first unexercised array element in order to get finer resolution with guaranteed monotonicity.

14. 发明申请

US20050093729A1 Guaranteed monotonic digital to analog converter 有权
标题翻译：保证单调的数模转换器
公开(公告)号：US20050093729A1
公开(公告)日：2005-05-05
申请号：US10916728
申请日：2004-08-12
申请人： Heng-Chih Lin , Chien-Chung Chen , Solti Peng
发明人： Heng-Chih Lin , Chien-Chung Chen , Solti Peng
IPC分类号： H03M1/06 , H03M1/12 , H03M1/66 , H03M1/68
CPC分类号： H03M1/0641 , H03M1/687
摘要： A hybrid Nyquist thermometer and sigma delta digital to analog converter is presented. The digital input signal is divided into most significant bits and least significant bits. The most significant bits are converted to a thermometer code. A thermometer element array is controlled by the thermometer code. A fractional value is calculated from the least significant bits and used to dither the first unexercised array element in order to get finer resolution with guaranteed monotonicity.
摘要翻译：提出了一种混合奈奎斯特温度计和西格玛delta数模转换器。数字输入信号被分为最高有效位和最低有效位。最高有效位被转换为温度计代码。温度计元件阵列由温度计代码控制。从最低有效位计算分数值，并用于抖动第一个未经排序的数组元素，以获得更精细的分辨率并保证单调性。

15. 发明授权

US6078524A High speed sensing circuit for a memory device 有权
标题翻译：用于存储器件的高速感测电路
公开(公告)号：US6078524A
公开(公告)日：2000-06-20
申请号：US206362
申请日：1998-12-07
申请人： Chien-Chung Chen
发明人： Chien-Chung Chen
IPC分类号： G11C16/28 , G11C16/04
CPC分类号： G11C16/28
摘要： A sensing circuit for sensing the binary state of a memory cell includes a first transistor wherein the first spaced-apart region is connected to a first voltage source, and the gate is connected to a second voltage source, a second transistor wherein the first spaced-apart region of the second transistor is connected to the second spaced-apart region of the first transistor, and a third transistor wherein the first spaced-apart region is connected to the second spaced-apart region of the second transistor, the gate is electrically connected to the memory cell, and the second spaced-apart region is connect to a ground potential. The circuit also includes a circuit to generate a first current in response to one binary state of the memory cell and a second current in response to another binary state of the memory cell wherein a feedback circuitry is created between the circuitry to generate currents and the second transistor, and a circuit to produce output signals in response to the first current and the second current.
摘要翻译：用于感测存储单元的二进制状态的感测电路包括第一晶体管，其中第一间隔区域连接到第一电压源，并且栅极连接到第二电压源，第二晶体管，其中第一间隔开的区域，第二晶体管的分开区域连接到第一晶体管的第二间隔区域，以及第三晶体管，其中第一间隔开的区域连接到第二晶体管的第二间隔开的区域，栅极电连接并且第二间隔开的区域连接到接地电位。电路还包括响应于存储器单元的一个二进制状态产生第一电流的电路和响应于存储单元的另一二进制状态的第二电流，其中在产生电流的电路之间产生反馈电路，而第二电流产生第二电流晶体管，以及响应于第一电流和第二电流产生输出信号的电路。

16. 发明授权

US6075726A High speed sensing circuit for a memory device 有权
标题翻译：用于存储器件的高速感测电路
公开(公告)号：US6075726A
公开(公告)日：2000-06-13
申请号：US206363
申请日：1998-12-07
申请人： Chien-Chung Chen
发明人： Chien-Chung Chen
IPC分类号： G11C16/28 , G11C16/06
CPC分类号： G11C16/28
摘要： A sensing circuit for sensing the binary state of a memory cell in a non-volatile memory device that includes an amplifier electrically connected to the memory cell and current generating circuitry connected to the amplifier for generating a first current in response to one binary state of the memory cell and a second current in response to another binary state of the memory cell. The sensing circuit also includes circuitry to speed initialization of the current generating circuitry and circuitry to prevent transient noise in the output of the sensing circuit during initialization of the current generating circuitry.
摘要翻译：一种感测电路，用于感测非易失性存储器件中的存储单元的二进制状态，该存储器单元包括电连接到存储单元的放大器和连接到放大器的电流产生电路，用于响应于第一电流的一个二进制状态产生第一电流存储单元和响应于存储单元的另一个二进制状态的第二电流。感测电路还包括用于加速电流发生电路和电路的初始化的电路，以在电流发生电路的初始化期间防止感测电路的输出中的瞬态噪声。

17. 发明授权

US5990486A Apparatus and method for measuring components of a solute stream 失效
标题翻译：用于测量溶质流的组分的装置和方法
公开(公告)号：US5990486A
公开(公告)日：1999-11-23
申请号：US976061
申请日：1997-11-21
申请人： Eric B. Chen , Chien-Chung Chen , Alfred A. Donatelli , Antonio Morales , Jason Barrett , William W. Bannister
发明人： Eric B. Chen , Chien-Chung Chen , Alfred A. Donatelli , Antonio Morales , Jason Barrett , William W. Bannister
IPC分类号： G01N21/85 , G05D11/13 , G01N15/06
CPC分类号： G05D11/138 , G01N21/85
摘要： The invention features an apparatus and method for determining and controlling the concentration of a solute in a solute stream by measuring the concentration of an indicator agent.
摘要翻译：本发明的特征在于通过测量指示剂浓度来确定和控制溶质流中溶质的浓度的装置和方法。

18. 外观设计

USD351678S Adjustable table lamp 失效
公开(公告)号：USD351678S
公开(公告)日：1994-10-18
申请号：US10147
申请日：1993-07-01
申请人： Chien-Chung Chen
设计人： Chien-Chung Chen

19. 发明授权

US09139935B2 Electrostatic-assisted fiber spinning method and production of highly aligned and packed hollow fiber assembly and membrane 有权
标题翻译：静电辅助纤维纺丝方法和高度排列和中空纤维组装和膜的生产
公开(公告)号：US09139935B2
公开(公告)日：2015-09-22
申请号：US12764692
申请日：2010-04-21
申请人： Chien-Chung Chen , Jen-Chang Yang , Jen-Chieh Lu , Sheng-Yang Lee
发明人： Chien-Chung Chen , Jen-Chang Yang , Jen-Chieh Lu , Sheng-Yang Lee
IPC分类号： A61F2/02 , D01D5/00 , B01D69/08 , D01D5/24 , D01F6/62 , D01F8/14 , A61F2/06 , B01D61/14
CPC分类号： D01D5/0069 , A61F2/06 , B01D61/147 , B01D69/08 , B01D2323/39 , D01D5/24 , D01F6/625 , D01F8/14 , Y10T428/249924
摘要： The invention provides a highly aligned and closely packed hollow fiber assembly, wherein the assemblies of fibrous membrane has a width-to-fiber diameter ratio (W/d) larger than 10 and the orientation of the fibers is no larger than +/−10°. Also provided is an electrospinning process for the preparation of the fiber assembly of the invention and its applications.
摘要翻译：本发明提供了一种高度排列紧密的中空纤维组件，其中纤维膜的组件具有大于10的宽度与纤维直径之比（W / d），并且纤维的取向不大于+/- 10 °。还提供了用于制备本发明的纤维组件及其应用的静电纺丝方法。

20. 发明申请

US20140362308A1 SUBSTRATE STRUCTURE AND TOUCH PANEL INCLUDING THE SAME 审中-公开
标题翻译：基板结构和触摸面板包括它们
公开(公告)号：US20140362308A1
公开(公告)日：2014-12-11
申请号：US14297629
申请日：2014-06-06
申请人： Chien-Chung Chen , Yi-Shu Chen , Hen-Ta Kang
发明人： Chien-Chung Chen , Yi-Shu Chen , Hen-Ta Kang
IPC分类号： G06F3/0354
CPC分类号： G06F3/041 , G06F2203/04103 , Y10T428/239 , Y10T428/30 , Y10T428/31678
摘要： A substrate structure is provided. The substrate structure includes a substrate, a first decoration layer, and a light absorption layer. The first decoration layer is disposed on the substrate. The light absorption layer is disposed on the first decoration layer, and the first decoration layer is located between the substrate and the light absorption layer. The material of the light absorption layer includes a semiconductor metal alloy.
摘要翻译：提供了基板结构。基板结构包括基板，第一装饰层和光吸收层。第一装饰层设置在基板上。光吸收层设置在第一装饰层上，第一装饰层位于基板和光吸收层之间。光吸收层的材料包括半导体金属合金。

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