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    • 12. 发明授权
    • Method and apparatus for managing medium access control (MAC) address
    • 用于管理媒体访问控制(MAC)地址的方法和装置
    • US07400623B2
    • 2008-07-15
    • US11142283
    • 2005-06-02
    • Chia-Hsin Chen
    • Chia-Hsin Chen
    • H04L12/56H04L12/43
    • H04L29/12009H04L29/12839H04L45/7453H04L49/90H04L49/901H04L61/6022
    • A method for managing medium access control (MAC) address and related apparatus are provided, including an MAC address learning method and an MAC addresses inquiring method. The learning method includes the steps of: mapping an MAC address to a designated slot and a companion slot in an address table; if said designated slot being empty, learning said MAC address into said designated slot; and if said designated slot being non-empty, said companion slot being empty and the content of said designated slot being non-static, moving the content of said designated slot to said companion slot and modifying a bit of the higher part of said MAC address in said companion slot and learning said MAC address into said designated slot.
    • 提供了一种用于管理介质访问控制(MAC)地址和相关装置的方法,包括MAC地址学习方法和MAC地址查询方法。 该学习方法包括以下步骤:将MAC地址映射到地址表中的指定时隙和伴随时隙; 如果所述指定的时隙是空的,则将所述MAC地址学习到所述指定的时隙中; 并且如果所述指定时隙不为空,则所述伴随时隙为空,并且所述指定时隙的内容是非静态的,将所述指定时隙的内容移动到所述伴随时隙,并修改所述MAC地址的较高部分的一位 在所述伴侣时隙中,将所述MAC地址学习到所述指定时隙。
    • 14. 发明授权
    • Memory address driver circuit
    • 内存地址驱动电路
    • US06370053B2
    • 2002-04-09
    • US09761880
    • 2001-01-17
    • Nai-Shung ChangChia-Hsin Chen
    • Nai-Shung ChangChia-Hsin Chen
    • G11C502
    • H05K1/0246G11C8/06G11C8/12H05K1/0262H05K1/14H05K1/141H05K2201/044H05K2201/10022H05K2201/10159
    • A memory address driver circuit with memory module slots on a computer main board that can be divided into two groups. One group of memory module slots includes the slots whose trace line to a control chipset is smaller than 2500 mils or closest to the control chipset. The other group of memory module slots includes all the remaining slots. The control chipset includes two memory control circuits. The memory control circuit for supporting DDR DRAM is connected to the address leads of the memory module slot closest to the control chipset. However, no terminal resistors are connected to any address leads of the memory module slot. Hence, engineers may have to design one set of terminal resistors only. In addition, the memory control circuit uses one-cycle access command timing to boost system performance.
    • 一个内存地址驱动电路,其内存模块插槽位于计算机主板上,可分为两组。 一组存储器模块插槽包括其控制芯片组的跟踪线小于2500密耳或最接近控制芯片组的插槽。 另一组内存模块插槽包括所有剩余的插槽。 控制芯片组包括两个存储器控制电路。 用于支持DDR DRAM的存储器控​​制电路连接到最靠近控制芯片组的存储器模块插槽的地址引线。 但是,没有端子电阻连接到内存模块插槽的任何地址引线。 因此,工程师可能只需要设计一组端子电阻。 此外,存储器控制电路使用一周期访问命令定时来提高系统性能。
    • 15. 发明申请
    • METHOD FOR PERFORMING BLOCK MANAGEMENT USING DYNAMIC THRESHOLD, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF
    • 使用动态阈值执行块管理的方法以及相关的存储器件及其控制器
    • US20110289260A1
    • 2011-11-24
    • US13014735
    • 2011-01-27
    • Chi-Lung WangChia-Hsin ChenChien-Cheng Lin
    • Chi-Lung WangChia-Hsin ChenChien-Cheng Lin
    • G06F12/00
    • G06F12/0246G06F12/10G06F2212/7201
    • A method for performing block management is provided. The method is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: adjusting a dynamic threshold according to at least one condition; and comparing a valid/invalid page count of a specific block of the plurality of blocks with the dynamic threshold to determine whether to erase the specific block. An associated memory device and a controller thereof are also provided, where the memory device includes the Flash memory and the controller. In particular, the controller includes a read only memory (ROM) arranged to store a program code, and further includes a microprocessor arranged to execute the program code to control access to the Flash memory and manage the plurality of blocks, where under control of the microprocessor, the controller operates according to the method.
    • 提供了一种执行块管理的方法。 该方法应用于闪速存储器的控制器,其中闪速存储器包括多个块。 该方法包括:根据至少一个条件调整动态阈值; 以及将所述多个块中的特定块的有效/无效页面计数与所述动态阈值进行比较,以确定是否擦除所述特定块。 还提供了一种相关联的存储器件及其控制器,其中存储器件包括闪存和控制器。 特别地,控制器包括被布置为存储程序代码的只读存储器(ROM),并且还包括微处理器,其被布置为执行程序代码以控制对闪存的访问并管理多个块,其中在 微处理器,控制器根据方法进行操作。
    • 19. 发明申请
    • MEMORY CARD AND METHOD FOR HANDLING DATA UPDATING OF A FLASH MEMORY
    • 用于处理闪存数据更新的存储卡和方法
    • US20090144488A1
    • 2009-06-04
    • US12050205
    • 2008-03-18
    • Chia-Hsin Chen
    • Chia-Hsin Chen
    • G06F12/02
    • G06F12/0246
    • The invention provides a method for handling data updating of a flash memory. In one embodiment, the flash memory comprises a mother block comprising a plurality of updated pages to be updated. First, a spare block, recording no data, is popped as a file allocation table (FAT) block corresponding to the mother block. Data for updating the updated pages of the mother block is then written to a plurality of replacing pages of the FAT block. Finally, a plurality of mapping relationships between the replacing pages and the updated pages are recorded in a page mapping table stored in the FAT block.
    • 本发明提供了一种处理闪速存储器的数据更新的方法。 在一个实施例中,闪速存储器包括母块,其包括要更新的多个更新的页面。 首先,将不记录数据的备用块作为与母块对应的文件分配表(FAT)块而弹出。 然后将用于更新母块的更新页面的数据写入FAT块的多个替换页面。 最后,替换页面和更新页面之间的多个映射关系被记录在存储在FAT块中的页面映射表中。