专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20050110983A1 Phase change memory devices with contact surface area to a phase changeable material defined by a sidewall of an electrode hole and methods of forming the same 有权
标题翻译：具有由电极孔的侧壁限定的相变材料的接触表面积的相变存储器件及其形成方法
公开(公告)号：US20050110983A1
公开(公告)日：2005-05-26
申请号：US10942187
申请日：2004-09-16
申请人： Won-Cheol Jeong , Hyeong-Jun Kim , Jae-Hyun Park , Chang-Wook Jeong
发明人： Won-Cheol Jeong , Hyeong-Jun Kim , Jae-Hyun Park , Chang-Wook Jeong
IPC分类号： H01L27/105 , G01C1/10 , G11C11/56 , G11C13/00 , H01L27/10 , H01L27/108 , H01L45/00
CPC分类号： H01L45/06 , H01L45/122 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1666
摘要： Phase change memory devices and methods of making phase changeable memory devices including a heating electrode disposed on a substrate are provided. The heating electrode includes an electrode hole in the heating electrode. A phase change material pattern is provided in the electrode hole and contacts a sidewall of the electrode hole. In some embodiments, the electrode hole extends through the heating electrode. In some embodiments, the phase changeable material pattern only contacts the electrode at a sidewall of the electrode hole
摘要翻译：提供了相变存储器件和制造包括设置在基板上的加热电极的相变存储器件的方法。加热电极在加热电极中包括电极孔。在电极孔中设置相变材料图案，并与电极孔的侧壁接触。在一些实施例中，电极孔延伸穿过加热电极。在一些实施例中，相变材料图案仅在电极孔的侧壁处接触电极

12. 发明申请

US20050078510A1 Magnetic random access memory devices including heat generating layers and related methods 有权
标题翻译：磁性随机存取存储器件包括发热层和相关方法
公开(公告)号：US20050078510A1
公开(公告)日：2005-04-14
申请号：US10795600
申请日：2004-03-08
申请人： Won-Cheol Jeong , Chang-Wook Jeong , Hyeong-Jun Kim , Jae-Hyun Park
发明人： Won-Cheol Jeong , Chang-Wook Jeong , Hyeong-Jun Kim , Jae-Hyun Park
IPC分类号： G11C11/15 , G11C11/00
CPC分类号： H01L43/08 , G11C11/15 , G11C11/1675 , H01L27/228
摘要： A magnetic random access memory device may include a first electrode on a substrate, a magnetic tunneling junction element electrically connected to the electrode, and a second electrode electrically connected to the first electrode through the magnetic tunneling junction element. In addition, a heat generating layer may be electrically connected in series between the first and second electrodes, and the heat generating layer may provide a relatively high resistance with respect to electrical current flow. Related methods are also discussed.
摘要翻译：磁性随机存取存储器件可以包括在衬底上的第一电极，电连接到电极的磁性隧道接合元件，以及通过磁性隧道结接合元件电连接到第一电极的第二电极。此外，发热层可以串联地电连接在第一和第二电极之间，并且发热层可以相对于电流流动提供相对较高的电阻。还讨论了相关方法。

13. 发明授权

US07651906B2 Integrated circuit devices having a stress buffer spacer and methods of fabricating the same 失效
标题翻译：具有应力缓冲垫片的集成电路器件及其制造方法
公开(公告)号：US07651906B2
公开(公告)日：2010-01-26
申请号：US11546120
申请日：2006-10-11
申请人： Jae-Hyun Park , Jae-Hee Oh , Won-Cheol Jeong , Sang-Jin Park
发明人： Jae-Hyun Park , Jae-Hee Oh , Won-Cheol Jeong , Sang-Jin Park
IPC分类号： H01L21/8234
CPC分类号： H01L27/24
摘要： Integrated circuit devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in the contact hole and a stress buffer spacer is provided between the vertical diode and the insulating layer. Methods of forming the integrated circuit devices are also provided.
摘要翻译：集成电路器件包括集成电路衬底和集成电路衬底上的绝缘层。接触孔穿透绝缘层。接触孔中有一个垂直二极管，在垂直二极管和绝缘层之间设有一个应力缓冲垫片。还提供了形成集成电路器件的方法。

14. 发明授权

US07622307B2 Semiconductor devices having a planarized insulating layer and methods of forming the same 失效
标题翻译：具有平坦化绝缘层的半导体器件及其形成方法
公开(公告)号：US07622307B2
公开(公告)日：2009-11-24
申请号：US11184701
申请日：2005-07-19
申请人： Jae-Hyun Park , Jae-Hee Oh , Won-Cheol Jeong
发明人： Jae-Hyun Park , Jae-Hee Oh , Won-Cheol Jeong
IPC分类号： H01L21/4763
CPC分类号： G11C11/16 , B82Y10/00 , G11C13/0004 , G11C2213/79 , H01L21/76819 , H01L27/228 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A semiconductor device includes at least one phase-change pattern disposed on a semiconductor substrate. A planarized capping layer, a planarized protecting layer, and a planarized insulating layer are sequentially stacked to surround sidewalls of the at least one phase-change pattern. An interconnection layer pattern is disposed on the planarized capping layer, the planarized protecting layer, and the planarized insulating layer. The interconnection layer pattern is in contact with the phase-change pattern.
摘要翻译：半导体器件包括设置在半导体衬底上的至少一个相变图案。依次层叠有平面化覆盖层，平坦化保护层和平坦化绝缘层，以包围至少一个相变图案的侧壁。互连层图案设置在平坦化覆盖层，平坦化保护层和平坦化绝缘层上。互连层图案与相变图案接触。

15. 发明授权

US07598112B2 Phase change memory devices and their methods of fabrication 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07598112B2
公开(公告)日：2009-10-06
申请号：US11392310
申请日：2006-03-28
申请人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
发明人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
IPC分类号： H01L29/04
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1666
摘要： In an embodiment, a phase change memory device includes a semiconductor substrate of a first conductivity type and a first interlayer insulating layer disposed on the semiconductor substrate. A hole penetrates the first interlayer insulating layer. A first and a second semiconductor pattern are sequentially stacked in a lower region of the hole. A cell electrode is provided on the second semiconductor pattern. The cell electrode has a lower surface than a top surface of the first interlayer insulating layer. A confined phase change material pattern fills the hole on the cell electrode. An upper electrode is disposed on the phase change material pattern. The phase change material pattern in the hole is self-aligned with the first and second semiconductor patterns by the hole. A method of fabricating the phase change memory device is also provided.
摘要翻译：在一个实施例中，相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的第一层间绝缘层。一个孔穿透第一层间绝缘层。第一和第二半导体图案顺序地堆叠在孔的下部区域中。电池电极设置在第二半导体图案上。电池电极具有比第一层间绝缘层的顶表面更低的表面。限制的相变材料图案填充电池电极上的孔。上电极设置在相变材料图案上。孔中的相变材料图案通过孔与第一和第二半导体图案自对准。还提供了一种制造相变存储器件的方法。

16. 发明授权

US07534723B2 Methods of forming fine patterns, and methods of forming trench isolation layers using the same 失效
标题翻译：形成精细图案的方法以及使用其形成沟槽隔离层的方法
公开(公告)号：US07534723B2
公开(公告)日：2009-05-19
申请号：US11519081
申请日：2006-09-11
申请人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
发明人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
IPC分类号： H01L21/76 , H01L21/027 , H01L21/033 , C03C25/68 , C23F1/00 , H01L21/302 , H01L21/461
CPC分类号： H01L21/32139 , H01L21/3086 , H01L21/3088 , H01L21/76224 , H01L21/76229 , H01L21/76838
摘要： Methods of forming a fine pattern include forming an underlying layer on a substrate, forming preliminary hard mask patterns having a first pitch on the underlying layer, the preliminary hard mask patterns having a first width and being spaced apart from each other by a second width smaller than the first width. The underlying layer is etched using the preliminary hard mask patterns as etch masks to thereby form preliminary underlying patterns. The preliminary hard mask patterns are pulled back, thereby forming hard mask patterns on the preliminary underlying patterns. An overlayer is formed on the substrate exposing top surfaces of the hard mask patterns. The hard mask patterns and the preliminary underlying patterns disposed below the hard mask patterns are etched using the overlayer as an etch mask, thereby forming underlying patterns having a second pitch smaller than the first pitch, and the overlayer is removed.
摘要翻译：形成精细图案的方法包括在基板上形成下层，在下层上形成具有第一间距的初步硬掩模图案，初步硬掩模图案具有第一宽度并且彼此间隔开第二宽度较小比第一宽。使用初步硬掩模图案作为蚀刻掩模蚀刻下层，从而形成初步的底层图案。初步硬掩模图案被拉回，从而在初始底层图案上形成硬掩模图案。在基板上形成覆盖层，暴露硬掩模图案的顶表面。使用覆盖层作为蚀刻掩模蚀刻设置在硬掩模图案之下的硬掩模图案和初始底层图案，由此形成具有小于第一间距的第二间距的下面的图案，并且去除覆盖层。

17. 发明授权

US07488981B2 Memory devices having sharp-tipped phase change layer patterns 有权
标题翻译：具有尖锐相变层图案的存储器件
公开(公告)号：US07488981B2
公开(公告)日：2009-02-10
申请号：US11018643
申请日：2004-12-21
申请人： Won-Cheol Jeong , Hyeong-Jun Kim , Jae-Hyun Park , Chang-Wook Jeong
发明人： Won-Cheol Jeong , Hyeong-Jun Kim , Jae-Hyun Park , Chang-Wook Jeong
IPC分类号： H01L27/108 , H01L29/00 , H01L31/036 , H01L31/112
CPC分类号： H01L45/06 , H01L45/122 , H01L45/1273 , H01L45/144 , H01L45/1675
摘要： Phase change Random Access Memory (PRAM) devices include a substrate and a phase change layer pattern on the substrate. The phase change layer pattern includes a sharp tip and at least one wall that extends from the sharp tip in a direction away from the substrate. At least one contact hole node is provided that contacts the phase change material pattern adjacent the sharp tip.
摘要翻译：相变随机存取存储器（PRAM）器件包括衬底和衬底上的相变层图案。相变层图案包括尖锐的尖端和至少一个壁，该壁从尖锐的尖端沿远离衬底的方向延伸。提供了与尖锐尖端相邻的相变材料图案的至少一个接触孔节点。

18. 发明申请

US20080160643A1 Magnetic Random Access Memory Cells Having Split Subdigit Lines Having Cladding Layers Thereon and Methods of Fabricating the Same 失效
标题翻译：磁性随机存取存储器单元分割具有包层的子数字线及其制作方法
公开(公告)号：US20080160643A1
公开(公告)日：2008-07-03
申请号：US12048082
申请日：2008-03-13
申请人： Jae-Hyun Park , Hyeong-Jun Kim , Won-Cheol Jeong , Chang-Wook Jeong , Hong-sik Jeong , Gi-Tae Jeong
发明人： Jae-Hyun Park , Hyeong-Jun Kim , Won-Cheol Jeong , Chang-Wook Jeong , Hong-sik Jeong , Gi-Tae Jeong
IPC分类号： H01L43/12
CPC分类号： H01L27/228 , B82Y10/00 , H01L43/08 , H01L43/12
摘要： Magnetic RAM cells have split sub-digit lines surrounded by cladding layers and methods of fabricating the same are provided. The magnetic RAM cells include first and second sub-digit lines formed over a semiconductor substrate. Only a bottom surface and an outer sidewall of the first sub-digit line are covered with a first cladding layer pattern. In addition, only a bottom surface and an outer sidewall of the second sub-digit line are covered with a second cladding layer pattern. The outer sidewall of the first sub-digit line is located distal from the second sub-digit line and the outer sidewall of the second sub-digit line is located distal the first sub-digit line. Methods of fabricating the magnetic RAM cells are also provided.
摘要翻译：磁性RAM单元具有由包覆层包围的分割的子数字线，并且提供其制造方法。磁性RAM单元包括在半导体衬底上形成的第一和第二子数字线。只有第一子数字线的底表面和外侧壁被第一覆层图案覆盖。此外，仅第二子数字线的底表面和外侧壁被第二包层图案覆盖。第一子数字线的外侧壁位于远离第二子数字线的位置，第二子数字线的外侧壁位于第一子数字线的远侧。还提供了制造磁性RAM单元的方法。

19. 发明申请

US20070076486A1 Phase change memory device and method of forming the same 有权
标题翻译：相变存储器件及其形成方法
公开(公告)号：US20070076486A1
公开(公告)日：2007-04-05
申请号：US11507573
申请日：2006-08-22
申请人： Won-Cheol Jeong , Se-Ho Lee , Jae-Hyun Park , Chang-Wook Jeong
发明人： Won-Cheol Jeong , Se-Ho Lee , Jae-Hyun Park , Chang-Wook Jeong
IPC分类号： G11C11/34
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/008 , G11C2213/52 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144
摘要： A PRAM and method of forming the same are disclosed. In various embodiments, the PRAM includes a lower insulation layer formed on a semiconductor substrate, a phase change material pattern formed on the lower insulation layer and a heating electrode contacting the phase change material pattern. The heating electrode can be formed of a material having a positive temperature coefficient such that specific resistance of the material increases as a function of temperature.
摘要翻译：公开了一种PRAM及其制造方法。在各种实施例中，PRAM包括形成在半导体衬底上的下绝缘层，形成在下绝缘层上的相变材料图案和与相变材料图案接触的加热电极。加热电极可以由具有正温度系数的材料形成，使得材料的电阻率随着温度的升高而增加。

20. 发明申请

US20070059934A1 Methods of forming fine patterns, and methods of forming trench isolation layers using the same 失效
标题翻译：形成精细图案的方法以及使用其形成沟槽隔离层的方法
公开(公告)号：US20070059934A1
公开(公告)日：2007-03-15
申请号：US11519081
申请日：2006-09-11
申请人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
发明人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/3086 , H01L21/3088 , H01L21/76224 , H01L21/76229 , H01L21/76838
摘要： Methods of forming a fine pattern include forming an underlying layer on a substrate, forming preliminary hard mask patterns having a first pitch on the underlying layer, the preliminary hard mask patterns having a first width and being spaced apart from each other by a second width smaller than the first width. The underlying layer is etched using the preliminary hard mask patterns as etch masks to thereby form preliminary underlying patterns. The preliminary hard mask patterns are pulled back, thereby forming hard mask patterns on the preliminary underlying patterns. An overlayer is formed on the substrate exposing top surfaces of the hard mask patterns. The hard mask patterns and the preliminary underlying patterns disposed below the hard mask patterns are etched using the overlayer as an etch mask, thereby forming underlying patterns having a second pitch smaller than the first pitch, and the overlayer is removed.
摘要翻译：形成精细图案的方法包括在基板上形成下层，在下层上形成具有第一间距的初步硬掩模图案，初步硬掩模图案具有第一宽度并且彼此间隔开第二宽度较小比第一宽。使用初步硬掩模图案作为蚀刻掩模蚀刻下层，从而形成初步的底层图案。初步硬掩模图案被拉回，从而在初始底层图案上形成硬掩模图案。在基板上形成覆盖层，暴露硬掩模图案的顶表面。使用覆盖层作为蚀刻掩模蚀刻设置在硬掩模图案之下的硬掩模图案和初始底层图案，由此形成具有小于第一间距的第二间距的下面的图案，并且去除覆盖层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式