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11. 发明授权

US07103722B2 Cache configuration for compressed memory systems 失效
标题翻译：压缩内存系统的缓存配置
公开(公告)号：US07103722B2
公开(公告)日：2006-09-05
申请号：US10200937
申请日：2002-07-22
申请人： Caroline Benveniste , Peter Franaszek , John T. Robinson , Charles Schulz
发明人： Caroline Benveniste , Peter Franaszek , John T. Robinson , Charles Schulz
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/0813 , G06F12/0864 , G06F2212/2542 , G06F2212/401
摘要： A method and structure is disclosed for constraining cache line replacement that processes a cache miss in a computer system. The invention contains a K-way set associative cache that selects lines in the cache for replacement. The invention constrains the selecting process so that only a predetermined subset of each set of cache lines is selected for replacement. The subset has at least a single cache line and the set size is at least two cache lines. The invention may further select between at least two cache lines based upon which of the cache lines was accessed least recently. A selective enablement of the constraining process is based on a free space memory condition of a memory associated with the cache memory. The invention may further constrain cache line replacement based upon whether the cache miss is from a non-local node in a nonuniform-memory-access system. The invention may also process cache writes so that a predetermined subset of each set is known to be in an unmodified state.
摘要翻译：公开了一种用于约束处理计算机系统中的高速缓存未命中的高速缓存行替换的方法和结构。本发明包含一个K路组合关联高速缓存，用于选择高速缓存中的行进行替换。本发明限制了选择过程，使得仅选择每组高速缓存行的预定子集用于替换。该子集具有至少一条缓存行，并且集合大小至少为两条缓存行。本发明还可以基于最近访问哪个高速缓存行，在至少两条高速缓存行之间进行选择。约束过程的选择性启用基于与高速缓存存储器相关联的存储器的空闲存储器条件。本发明还可以基于高速缓存未命中来自非均匀存储器访问系统中的非本地节点来进一步约束高速缓存行替换。本发明还可以处理高速缓存写入，使得每组的预定子集已知处于未修改状态。

12. 发明申请

US20050050404A1 Apparatus and method for detecting and forecasting resource bottlenecks 有权
标题翻译：检测和预测资源瓶颈的装置和方法
公开(公告)号：US20050050404A1
公开(公告)日：2005-03-03
申请号：US10647800
申请日：2003-08-25
申请人： Vittorio Castelli , Peter Franaszek , Luis Lastras
发明人： Vittorio Castelli , Peter Franaszek , Luis Lastras
IPC分类号： G06F11/00 , G06F11/34
CPC分类号： G06F11/3409 , G06F11/3452 , G06F2201/81
摘要： A system and method of detecting and forecasting resource bottlenecks of a computer system. In one aspect, a method comprises the steps of: monitoring with successive measurements a utilization parameter of a system resource; computing a change parameter by comparing the differences between successive measurements of the utilization parameter; comparing the change parameter to a threshold change parameter; and reporting a resource bottleneck if the change parameter exceeds the threshold change parameter.
摘要翻译：一种检测和预测计算机系统资源瓶颈的系统和方法。一方面，一种方法包括以下步骤：通过连续测量监视系统资源的利用参数; 通过比较使用参数的连续测量之间的差异来计算变化参数; 将变化参数与阈值变化参数进行比较; 并且如果改变参数超过阈值变化参数则报告资源瓶颈。

13. 发明授权

US07904660B2 Page descriptors for prefetching and memory management 有权
标题翻译：页面描述符用于预取和内存管理
公开(公告)号：US07904660B2
公开(公告)日：2011-03-08
申请号：US11844086
申请日：2007-08-23
申请人： Peter Franaszek
发明人： Peter Franaszek
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6022 , G06F2212/6024
摘要： A computer system and a method for enhancing the cache prefetch behavior. A computer system including a processor, a main memory, a prefetch controller, a cache memory, a prefetch buffer, and a main memory, wherein each page in the main memory has associated with it a tag, which is used for controlling the prefetching of a variable subset of lines from this page as well as lines from at least one other page. And, coupled to the processor is a prefetch controller, wherein the prefetch controller responds to the processor determining a fault (or miss) occurred to a line of data by fetching a corresponding line of data with the corresponding tag, with the corresponding tag to be stored in the prefetch buffer, and sending the corresponding line of data to the cache memory.
摘要翻译：一种用于增强缓存预取行为的计算机系统和方法。一种包括处理器，主存储器，预取控制器，高速缓冲存储器，预取缓冲器和主存储器的计算机系统，其中，主存储器中的每个页面与其相关联，该标签用于控制预取来自该页面的行的可变子集以及至少一个其他页面的行。并且，耦合到处理器的是预取控制器，其中预取控制器响应于处理器确定一行数据发生的故障（或未命中），通过相应的标签获取相应的数据行，相应的标签为存储在预取缓冲器中，并将相应的数据行发送到高速缓冲存储器。

14. 发明申请

US20080059714A1 SYSTEM, METHOD AND STORAGE MEDIUM FOR PREFETCHING VIA MEMORY BLOCK TAGS 有权
标题翻译：用于通过存储块标签进行预制的系统，方法和存储介质
公开(公告)号：US20080059714A1
公开(公告)日：2008-03-06
申请号：US11936414
申请日：2007-11-07
申请人： Peter Franaszek , Luis Lastras
发明人： Peter Franaszek , Luis Lastras
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0862
摘要： A system for memory management including a tag cache in communication with one or more cache devices in a storage hierarchy is provided. The tag cache includes tags of recently accessed memory blocks, each tag corresponding to one of the memory blocks and each tag including tag contents. The tag contents include a memory block real address and one bit for every memory line in the memory block. The bits are referred to as prefetch bits. Each of the prefetch bits is reset to a non-prefetch status with a selected probability of between zero and one. The tag contents control which memory lines of the corresponding memory block are prefetched into at least one of the cache devices. The tag contents are updated using a selected subset of processor references. The subset is referred to as filtered references. The tag contents are modified probabilistically at selected times or events.
摘要翻译：提供了一种用于存储器管理的系统，其包括与存储层级中的一个或多个高速缓存设备通信的标签高速缓存。标签缓存包括最近访问的存储块的标签，每个标签对应于一个存储器块，每个标签包括标签内容。标签内容包括存储器块实际地址和存储器块中每个存储器线的一位。这些位被称为预取位。每个预取位被复位到具有0和1之间的所选概率的非预取状态。标签内容控制对应的存储器块的哪些存储器行被预取到至少一个高速缓存器件中。使用选定的处理器引用子集来更新标签内容。该子集称为过滤引用。标签内容在选定的时间或事件中被概率地修改。

15. 发明申请

US20070226428A1 Computer compressed memory system and method for storing and retrieving data in a processing system 失效
标题翻译：计算机压缩存储器系统和用于在处理系统中存储和检索数据的方法
公开(公告)号：US20070226428A1
公开(公告)日：2007-09-27
申请号：US11369987
申请日：2006-03-08
申请人： Robert Tremaine , Peter Franaszek
发明人： Robert Tremaine , Peter Franaszek
IPC分类号： G06F13/00
CPC分类号： G06F13/16 , G06F12/0802 , G06F12/10
摘要： A computer compressed memory system for storing and retrieving data in a processing system, includes a memory including at least one memory device for storing at least one of uncompressed data and compressed data, a compressor for encoding data blocks into smaller compressed data blocks for storage in the memory, a decompressor for reconstituting encoded data into original uncompressed data blocks, a memory controller for generating, receiving and responding to memory access requests from processing and input/output units and responsively controlling access to the memory from the compressor and the decompressor for storing and retrieving data, and a hardware priority filter associated with the memory controller for selecting specific memory access requests according to attributes and access type within prescribed rates and under specific conditions.
摘要翻译：一种用于在处理系统中存储和检索数据的计算机压缩存储器系统，包括存储器，其包括用于存储未压缩数据和压缩数据中的至少一个的至少一个存储器设备，用于将数据块编码为较小压缩数据块以用于存储的压缩器存储器，用于将编码数据重构成原始未压缩数据块的解压缩器，存储器控制器，用于生成，接收和响应来自处理和输入/输出单元的存储器访问请求，以及响应地控制来自压缩器和解压缩器的存储器的存取以及检索数据，以及与所述存储器控制器相关联的硬件优先级过滤器，用于根据规定速率内的特定条件下的属性和访问类型来选择特定存储器访问请求。

16. 发明申请

US20060106991A1 Victim prefetching in a cache hierarchy 失效
标题翻译：受害者在缓存层次结构中预取
公开(公告)号：US20060106991A1
公开(公告)日：2006-05-18
申请号：US10989997
申请日：2004-11-16
申请人： Peter Franaszek , Steven Kunkel , Luis Lastras Montano , Aaron Sawdey
发明人： Peter Franaszek , Steven Kunkel , Luis Lastras Montano , Aaron Sawdey
IPC分类号： G06F12/00
CPC分类号： G06F12/122 , G06F12/0862 , G06F12/0897
摘要： We present a “directory extension” (hereinafter “DX”) to aid in prefetching between proximate levels in a cache hierarchy. The DX may maintain (1) a list of pages which contains recently ejected lines from a given level in the cache hierarchy, and (2) for each page in this list, the identity of a set of ejected lines, provided these lines are prefetchable from, for example, the next level of the cache hierarchy. Given a cache fault to a line within a page in this list, other lines from this page may then be prefetched without the substantial overhead to directory lookup which would otherwise be required.
摘要翻译：我们提出一个“目录扩展名”（以下简称“DX”）来辅助缓存层级中的邻近级别之间的预取。 DX可以维护（1）包含最近从缓存层级中的给定级别排出的行的页面列表，以及（2）对于该列表中的每个页面，提供这些行是可预取的集合的标识从例如缓存层次结构的下一级。给定列表中页面内的行的高速缓存错误，然后可以预取此页面中的其他行，而不需要大量开销，否则将需要目录查找。

17. 发明申请

US20060106870A1 Data compression using a nested hierarchy of fixed phrase length dictionaries 审中-公开
标题翻译：使用固定短语长度字典的嵌套层次结构进行数据压缩
公开(公告)号：US20060106870A1
公开(公告)日：2006-05-18
申请号：US10989690
申请日：2004-11-16
申请人： Peter Franaszek , Luis Montano , John Robinson
发明人： Peter Franaszek , Luis Montano , John Robinson
IPC分类号： G06F17/00 , G06F7/00
CPC分类号： H03M7/3088
摘要： Exemplary embodiments are described herein whereby blocks of data are losslessly compressed and decompressed using a nested hierarchy of fixed phrase length dictionaries. The dictionaries may be built using information related to the manner in which data is commonly organized in computer systems for convenient retrieval, processing, and storage. This results in low cost designs that give significant compression. Further, the methods can be implemented very efficiently in hardware.
摘要翻译：本文描述了示例性实施例，其中使用固定短语长度字典的嵌套层级对数据块进行无损压缩和解压缩。可以使用与计算机系统中通常组织数据的方式相关的信息来构建词典，以便于检索，处理和存储。这导致了低成本设计，给出显着的压缩。此外，可以在硬件中非常有效地实现这些方法。

18. 发明申请

US20050235115A1 SYSTEM, METHOD AND STORAGE MEDIUM FOR MEMORY MANAGEMENT 失效
标题翻译：用于内存管理的系统，方法和存储介质
公开(公告)号：US20050235115A1
公开(公告)日：2005-10-20
申请号：US10709128
申请日：2004-04-15
申请人： Peter Franaszek , Luis Lastras
发明人： Peter Franaszek , Luis Lastras
IPC分类号： G06F12/08 , G06F12/00 , G06F12/12
CPC分类号： G06F12/0862 , G06F12/0895 , G06F2212/1024 , G06F2212/502 , G06F2212/6022 , G06F2212/6024
摘要： A system for memory management including a tag controlled buffer in communication with a memory device. The memory device includes a plurality of pages divided into a plurality of individually addressable lines. The tag controlled buffer includes a prefetch buffer including at least one of the individually addressable lines from the memory device. The tag controlled buffer also includes a tag cache in communication with the prefetch buffer. The tag cache includes a plurality of tags, where each tag is associated with one of the pages in the memory device and each tag includes a pointer to at least one of the lines in the prefetch buffer. Access to the lines in the prefetch buffer is controlled by the tag cache.
摘要翻译：一种用于存储器管理的系统，包括与存储器件通信的标签控制缓冲器。存储装置包括被分成多个可单独寻址的行的多个页面。标签控制缓冲器包括预取缓冲器，其包括来自存储器装置的至少一个可单独寻址的线路。标签控制缓冲器还包括与预取缓冲器通信的标签缓存。标签缓存包括多个标签，其中每个标签与存储器设备中的一个页面相关联，并且每个标签包括指向预取缓冲器中的至少一行的指针。访问预取缓冲区中的行由标记缓存控制。

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