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11. 发明申请

US20160284119A1 Hardware Based Free Lists for Multi-Rate Shader 审中-公开
标题翻译：基于硬件的多速率着色器的免费列表
公开(公告)号：US20160284119A1
公开(公告)日：2016-09-29
申请号：US14666463
申请日：2015-03-24
申请人： Prasoonkumar Surti , Thomas A. Piazza
发明人： Prasoonkumar Surti , Thomas A. Piazza
IPC分类号： G06T15/80 , G06T17/10 , G06T1/60
CPC分类号： G06T1/60 , G06T15/005 , G06T15/80
摘要： A group of buffers are connected via pointers as free-lists implemented in hardware, such that shader information and output processing information can be efficiently accessed by a multi-rate shader. A free-list storage picks the first available entry. The first free entry that gets allocated then becomes a pointer to another entry.
摘要翻译：一组缓冲器通过指针作为在硬件中实现的自由列表连接，使得可以通过多速率着色器有效地访问着色器信息和输出处理信息。免费列表存储选择第一个可用条目。获得分配的第一个空闲条目将成为另一条目的指针。

12. 发明授权

US09235926B2 Techniques for improving MSAA rendering efficiency 有权
标题翻译：提高MSAA渲染效率的技术
公开(公告)号：US09235926B2
公开(公告)日：2016-01-12
申请号：US13726362
申请日：2012-12-24
申请人： Prasoonkumar Surti , Thomas A. Piazza
发明人： Prasoonkumar Surti , Thomas A. Piazza
IPC分类号： G06T15/00 , G06T15/50 , G06T11/40
CPC分类号： G06T15/503 , G06T11/40 , G06T15/005 , G06T2200/12 , G06T2210/08
摘要： Various embodiments are generally directed to techniques for causing the storage of a color data value of a clear color to be deferred as rendered color data values are stored for samples. A device comprises a processor circuit and a storage to store instructions that cause the processor circuit to render a pixel from multiple samples taken of a three-dimensional model of an object, the pixel corresponding to a pixel sample data which comprises multiple color storage locations that are each identified by a numeric identifier, and which comprises multiple sample color indices that each correspond to a sample to point to at least one color storage location; and allocate color storage locations in an order selected to define a subset of possible combinations of binary index values among all of the sample color indices as invalid combinations. Other embodiments are described and claimed.
摘要翻译：各种实施例通常涉及用于在为样本存储所渲染的颜色数据值时使得清除颜色的颜色数据值的存储被延迟的技术。一种设备包括处理器电路和存储器，用于存储使得处理器电路从取自对象的三维模型的多个样本呈现像素的指令，所述像素对应于包括多个颜色存储位置的像素样本数据，每个由数字标识符标识，并且其包括多个样本颜色索引，每个样本颜色索引对应于样本以指向至少一个颜色存储位置; 并且以所选择的顺序分配颜色存储位置，以将所有样本颜色索引中的二进制索引值的可能组合的子集定义为无效组合。描述和要求保护其他实施例。

13. 发明申请

US20140347385A1 LOSSY COLOR MERGE FOR MULTI-SAMPLING ANTI-ALIASING COMPRESSION 有权
标题翻译：用于多采样抗锯齿压缩的丢失颜色合成
公开(公告)号：US20140347385A1
公开(公告)日：2014-11-27
申请号：US13901117
申请日：2013-05-23
申请人： Tomas G. Akenine-Moller , Thomas A. Piazza , Prasoonkumar Surti
发明人： Tomas G. Akenine-Moller , Thomas A. Piazza , Prasoonkumar Surti
IPC分类号： G06T5/00
CPC分类号： G06T5/002 , G06T9/00 , G06T11/40 , G06T15/503
摘要： Techniques related to graphics rendering including lossy color merge for multi-sampling anti-aliasing compression are discussed.
摘要翻译：讨论了与图形渲染相关的技术，包括用于多采样抗锯齿压缩的有损颜色合并。

14. 发明授权

US08836712B2 Filtering mechanism for render target line modification 有权
标题翻译：渲染目标线修改的过滤机制
公开(公告)号：US08836712B2
公开(公告)日：2014-09-16
申请号：US13004950
申请日：2011-01-12
申请人： Prasoonkumar Surti
发明人： Prasoonkumar Surti
IPC分类号： G09G5/36 , G06T1/60
CPC分类号： G06F12/0895 , G06F2212/401 , G06F2212/455 , G06T1/60 , G06T2200/28 , G09G5/36 , G09G5/363 , G09G2340/02 , G09G2360/121 , G09G2360/122
摘要： Modification messages may be filtered to reduce the load on a message channel between a render cache and a frame buffer compression. A group of cache lines may be checked to see whether both a subspan request hits an unlit bit and a modify message was already sent. If so, the modification message may be filtered.
摘要翻译：可以对修改消息进行过滤，以减少渲染缓存和帧缓冲区压缩之间的消息通道的负载。可以检查一组高速缓存行，以查看子跨越请求是否触发不亮位，并且已经发送修改消息。如果是这样，可以对修改消息进行过滤。

15. 发明授权

US07719540B2 Render-cache controller for multithreading, multi-core graphics processor 有权
标题翻译：用于多线程，多核图形处理器的渲染缓存控制器
公开(公告)号：US07719540B2
公开(公告)日：2010-05-18
申请号：US10816052
申请日：2004-03-31
申请人： Thomas A. Piazza , Prasoonkumar Surti
发明人： Thomas A. Piazza , Prasoonkumar Surti
IPC分类号： G09G5/36 , G06F15/00 , G06T1/00
CPC分类号： G09G5/363 , G06F12/0804 , G06F12/0875 , G06T15/005
摘要： A method and apparatus for rendering three-dimensional graphics using a streaming render-cache with a multi-threading, multi-core graphics processor are disclosed. The graphics processor includes a streaming render-cache and render-cache controller to maintain the order in which threads are dispatched to the graphics engine, and to maintain data coherency between the render-cache and the main memory. The render-cache controller blocks threads from being dispatched to the graphics engine out of order by only allowing one sub-span to be in-flight at any given time.
摘要翻译：公开了一种使用具有多线程，多核图形处理器的流渲染缓存来呈现三维图形的方法和装置。图形处理器包括流渲染缓存和渲染缓存控制器，用于维护线程被分配到图形引擎的顺序，并且保持渲染缓存和主存储器之间的数据一致性。渲染缓存控制器通过仅允许一个子跨度在任何给定时间在飞行中来阻止线程被分派到图形引擎。

16. 发明授权

US07320053B2 Banking render cache for multiple access 有权
标题翻译：银行渲染缓存用于多次访问
公开(公告)号：US07320053B2
公开(公告)日：2008-01-15
申请号：US10969877
申请日：2004-10-22
申请人： Prasoonkumar Surti , Brian Ruttenberg , Aditya Navale
发明人： Prasoonkumar Surti , Brian Ruttenberg , Aditya Navale
IPC分类号： G06F12/00
CPC分类号： G06F12/0851 , G06F12/0875 , Y02D10/13
摘要： A cache memory system may be is organized as a set of numbered banks. If two clients need to access the cache, a contention situation may be resolved by a contention resolution process. The contention resolution process may be based on relative priorities of the clients.
摘要翻译：缓存存储器系统可以被组织为一组编号的存储体。如果两个客户端需要访问缓存，则争用解决过程可能会解决争用情况。争用解决过程可以基于客户端的相对优先级。

17. 发明授权

US11010953B2 Dedicated fixed point blending for energy efficiency 有权
公开(公告)号：US11010953B2
公开(公告)日：2021-05-18
申请号：US15493195
申请日：2017-04-21
申请人： Abhishek R. Appu , Prasoonkumar Surti , Srivallaba Mysore , Subhajit Dasgupta , Hiroshi Akiba , Eric J. Hoekstra , Linda L. Hurd , Travis T. Schluessler , Daren J. Schmidt
发明人： Abhishek R. Appu , Prasoonkumar Surti , Srivallaba Mysore , Subhajit Dasgupta , Hiroshi Akiba , Eric J. Hoekstra , Linda L. Hurd , Travis T. Schluessler , Daren J. Schmidt
IPC分类号： G06T15/00 , G06T15/50 , G06T1/20 , G06F1/3287 , G06F9/54
摘要： Briefly, in accordance with one or more embodiments, a processor receives an incoming data stream that includes alpha channel data, and a memory stores an application programming interface (API). The API is to route the alpha channel data to a fixed point blending unit to perform one or more blending operations using fixed point representation of the alpha channel data. The API is further to route the incoming data stream to a floating point blending unit to perform operations involving floating point representation of the incoming data.

18. 发明申请

US20190244418A1 CONDITIONAL SHADER FOR GRAPHICS 审中-公开
公开(公告)号：US20190244418A1
公开(公告)日：2019-08-08
申请号：US16269270
申请日：2019-02-06
申请人： Prasoonkumar Surti , Karthik Vaidyanathan , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh , Devan Burke , Philip R. Laws , Subramaniam Maiyuran , Abhishek R. Appu , ElMoustapha Ould-Ahmed-Vall , Peter L. Doyle
发明人： Prasoonkumar Surti , Karthik Vaidyanathan , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh , Devan Burke , Philip R. Laws , Subramaniam Maiyuran , Abhishek R. Appu , ElMoustapha Ould-Ahmed-Vall , Peter L. Doyle
IPC分类号： G06T15/80 , G06F9/50 , G06T1/20 , G06T5/20
CPC分类号： G06T15/80 , G06F9/50 , G06F9/5011 , G06T1/20 , G06T5/20
摘要： An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.

19. 发明申请

US20180307487A1 GRAPHICS CONTROL FLOW MECHANISM 审中-公开
公开(公告)号：US20180307487A1
公开(公告)日：2018-10-25
申请号：US15493442
申请日：2017-04-21
申请人： Subramaniam M. Maiyuran , Guei-Yuan Lueh , Supratim Pal , Gang Chen , Ananda V. Kommaraju , Joy Chandra , Altug Koker , Prasoonkumar Surti , David Puffer , Hong Bin Liao , Joydeep Ray , Abhishek R. Appu , Ankur N. Shah , Travis T. Schluessler , Jonathan Kennedy , Devan Burke
发明人： Subramaniam M. Maiyuran , Guei-Yuan Lueh , Supratim Pal , Gang Chen , Ananda V. Kommaraju , Joy Chandra , Altug Koker , Prasoonkumar Surti , David Puffer , Hong Bin Liao , Joydeep Ray , Abhishek R. Appu , Ankur N. Shah , Travis T. Schluessler , Jonathan Kennedy , Devan Burke
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06T1/20
摘要： An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.

20. 发明申请

US20180285374A1 ENGINE TO ENABLE HIGH SPEED CONTEXT SWITCHING VIA ON-DIE STORAGE 审中-公开
公开(公告)号：US20180285374A1
公开(公告)日：2018-10-04
申请号：US15477027
申请日：2017-04-01
申请人： Altug Koker , Prasoonkumar Surti , David Puffer , Subramaniam Maiyuran , Guei-Yuan Lueh , Abhishek R. Appu , Joydeep Ray , Balaji Vembu , Tomer Bar-On , Andrew T. Lauritzen , Hugues Labbe , John G. Gierach , Gabor Liktor
发明人： Altug Koker , Prasoonkumar Surti , David Puffer , Subramaniam Maiyuran , Guei-Yuan Lueh , Abhishek R. Appu , Joydeep Ray , Balaji Vembu , Tomer Bar-On , Andrew T. Lauritzen , Hugues Labbe , John G. Gierach , Gabor Liktor
IPC分类号： G06F17/30 , G06F9/38 , G06F9/30
摘要： In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

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