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11. 发明授权

US08656213B2 Implementing storage adapter performance optimization with chained hardware operations and error recovery firmware path 失效
标题翻译：通过链接的硬件操作和错误恢复固件路径实现存储适配器性能优化
公开(公告)号：US08656213B2
公开(公告)日：2014-02-18
申请号：US13114354
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F11/00
CPC分类号： G06F11/0727 , G06F3/061 , G06F3/0658 , G06F3/0659 , G06F3/0689 , G06F11/0793
摘要： A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to minimize hardware and firmware interactions and a bridge code configured to select a firmware sequence for error recovery to complete the operations responsive to an identified error in the predefined chain, and a design structure on which the subject controller circuit resides are provided. A selected predefined chain is configured to implement a particular performance path to maximize performance. Responsive to an identified predefined error during hardware operations in the predefined hardware chain, a bridge code is configured to select a non-performance path firmware sequence for error recovery completion of remaining operations.
摘要翻译：一种用于利用预定义的硬件操作链来实现存储适配器性能优化的方法和控制器，其被配置为最小化硬件和固件交互以及配置成选择用于错误恢复的固件序列的桥接代码，以响应于所述预定链中的所识别的错误来完成操作，并且设置有主体控制器电路所在的设计结构。所选择的预定义链被配置为实现特定的性能路径以最大化性能。响应于在预定义硬件链中的硬件操作期间识别的预定义错误，桥接代码被配置为选择用于其余操作的错误恢复完成的非性能路径固件序列。

12. 发明授权

US08544029B2 Implementing storage adapter performance optimization with chained hardware operations minimizing hardware/firmware interactions 有权
标题翻译：通过链接的硬件操作实现存储适配器性能优化，从而最大限度地减少硬件/固件交互
公开(公告)号：US08544029B2
公开(公告)日：2013-09-24
申请号：US13114107
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F9/44 , G06F13/28
CPC分类号： G06F3/0611 , G06F3/0656 , G06F3/0689
摘要： A method and controller for implementing storage adapter performance optimization with chained hardware operations minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and one or more processors. An event queue is coupled to at least one processor notifying the processor of a plurality of predefined events. A control block is designed to control an operation in one of the plurality of hardware engines including the hardware engine writing an event queue entry. A plurality of the control blocks are selectively arranged in a predefined chain to minimize the hardware engine writing event queue entries to the processor.
摘要翻译：一种用于实现存储适配器性能优化的方法和控制器，其具有最小化硬件和固件交互的链接硬件操作，以及提供主题控制器电路所在的设计结构。控制器包括多个硬件引擎; 和一个或多个处理器。事件队列被耦合到至少一个处理器通知多个预定义事件的处理器。控制块被设计成控制多个硬件引擎中的一个的操作，包括写入事件队列条目的硬件引擎。多个控制块被选择性地布置在预定义的链中以最小化硬件引擎将事件队列条目写入处理器。

13. 发明申请

US20120304001A1 IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CHAINED HARDWARE OPERATIONS AND ERROR RECOVERY FIRMWARE PATH 失效
标题翻译：实施存储适配器性能优化与链接硬件操作和错误恢复固件路径
公开(公告)号：US20120304001A1
公开(公告)日：2012-11-29
申请号：US13114354
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F11/20
CPC分类号： G06F11/0727 , G06F3/061 , G06F3/0658 , G06F3/0659 , G06F3/0689 , G06F11/0793
摘要： A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to minimize hardware and firmware interactions and a bridge code configured to select a firmware sequence for error recovery to complete the operations responsive to an identified error in the predefined chain, and a design structure on which the subject controller circuit resides are provided. A selected predefined chain is configured to implement a particular performance path to maximize performance. Responsive to an identified predefined error during hardware operations in the predefined hardware chain, a bridge code is configured to select a non-performance path firmware sequence for error recovery completion of remaining operations.
摘要翻译：一种用于利用预定义的硬件操作链来实现存储适配器性能优化的方法和控制器，其被配置为最小化硬件和固件交互以及配置成选择用于错误恢复的固件序列的桥接代码，以响应于所述预定链中的所识别的错误来完成操作，并且设置有主体控制器电路所在的设计结构。所选择的预定义链被配置为实现特定的性能路径以最大化性能。响应于在预定义硬件链中的硬件操作期间识别的预定义错误，桥接代码被配置为选择用于其余操作的错误恢复完成的非性能路径固件序列。

14. 发明申请

US20120303922A1 IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH ENHANCED RESOURCE POOL ALLOCATION 有权
标题翻译：实施存储适配器性能优化与增强资源池分配
公开(公告)号：US20120303922A1
公开(公告)日：2012-11-29
申请号：US13114427
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F12/02
CPC分类号： G06F3/0617 , G06F3/0631 , G06F3/0689
摘要： A method and controller for implementing storage adapter performance optimization with enhanced resource pool allocation, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; a processor, and a plurality of resource pools. A plurality of work queues is associated with the resource pools. The processor initializes a list of types, and the associated amount of pages for each allocate type. The hardware engines maintain a count of allocate types, specifying a type on each allocation and deallocation, and performing allocation from the resource pools for deadlock avoidance.
摘要翻译：一种用于实现具有增强的资源池分配的存储适配器性能优化的方法和控制器，以及提供了主题控制器电路所在的设计结构。控制器包括多个硬件引擎; 处理器和多个资源池。多个工作队列与资源池相关联。处理器初始化类型列表，以及每种分配类型的相关联的页面数量。硬件引擎维护分配类型的计数，指定每个分配和解除分配的类型，并从资源池执行死锁避免的分配。

15. 发明授权

US08868828B2 Implementing storage adapter performance optimization with cache data/directory mirroring 有权
标题翻译：使用缓存数据/目录镜像实现存储适配器性能优化
公开(公告)号：US08868828B2
公开(公告)日：2014-10-21
申请号：US13114185
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/00 , G06F11/108 , G06F11/2071 , G06F12/08 , G06F12/0868 , G06F2211/1009 , G06F2211/1059 , G06F2212/1016 , G06F2212/225 , G06F2212/286
摘要： A method and controller for implementing storage adapter performance optimization with cache data and cache directory mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. One of the first controller or the second controller operates in a first initiator mode includes firmware to set up an initiator write operation building a data frame for transferring data and a respective cache line (CL) for each page index to the other controller operating in a second target mode. Respective initiator hardware engines transfers data, reading CLs from an initiator control store, and writing updated CLs to an initiator data store, and simultaneously sends data and updated CLs to the other controller. Respective target hardware engines write data and updated CLs to the target data store, eliminating firmware operations of the controller operating in the second target mode.
摘要翻译：一种用于实现存储适配器性能优化的方法和控制器，其中缓存数据和双重适配器之间的缓存目录镜像最小化固件操作，以及提供主题控制器电路所在的设计结构。第一控制器或第二控制器中的一个以第一启动器模式操作，包括固件，用于建立向每个页索引建立数据帧的启动器写入操作和用于每个页索引的相应高速缓存行（CL）到另一控制器第二目标模式。各发起者硬件引擎传送数据，从启动器控制存储器读取CL，并将更新后的CL写入发起者数据存储器，同时向其他控制器发送数据和更新的CL。各个目标硬件引擎将数据和更新的CL写入目标数据存储，消除了在第二目标模式下操作的控制器的固件操作。

16. 发明申请

US20120303909A1 IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH ENHANCED HARDWARE AND SOFTWARE INTERFACE 失效
标题翻译：使用增强硬件和软件界面实现存储适配器性能优化
公开(公告)号：US20120303909A1
公开(公告)日：2012-11-29
申请号：US13114390
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F12/00
CPC分类号： G06F3/0689 , G06F3/0611 , G06F3/0658 , G06F3/0659 , G06F11/108 , G06F2211/1009
摘要： A method and controller for implementing storage adapter performance optimization with chained hardware operations and an enhanced hardware (HW) and firmware (FW) interface minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a processor. A data store is configured to store a plurality of control blocks. A global work queue includes a plurality of the control blocks selectively arranged in a predefined chain to define sequences of hardware operations. The global work queue includes a queue input coupled to the processor and the hardware engines and an output coupled to the hardware engines. The control blocks are arranged in respective engine work queues designed to control hardware operations of the respective hardware engines and respective control blocks are arranged in an event queue to provide completion results to the processor.
摘要翻译：一种用于实现具有链接硬件操作的存储适配器性能优化的方法和控制器以及最小化硬件和固件交互的增强的硬件（HW）和固件（FW）接口，以及提供主题控制器电路所在的设计结构。控制器包括多个硬件引擎; 和处理器。数据存储器被配置为存储多个控制块。全局工作队列包括选择性地布置在预定义链中以定义硬件操作序列的多个控制块。全局工作队列包括耦合到处理器和硬件引擎的队列输入以及耦合到硬件引擎的输出。控制块被布置在各自的引擎工作队列中，其被设计成控制各个硬件引擎的硬件操作，并且各个控制块被布置在事件队列中以向处理器提供完成结果。

17. 发明申请

US20120303886A1 IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH HARDWARE CHAINS TO SELECT PERFORMANCE PATH 失效
标题翻译：实施存储适配器性能优化与硬件链选择性能路径
公开(公告)号：US20120303886A1
公开(公告)日：2012-11-29
申请号：US13114291
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F3/061 , G06F3/0658 , G06F3/0659 , G06F3/0689 , G06F12/0866
摘要： A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to implement a particular performance path minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a data store configured to store a plurality of control blocks selectively arranged in one of a plurality of predefined chains. Each predefined chain defines a sequence of operations. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A resource handle structure is configured to select a predefined chain based upon a particular characteristic of the system. Each predefined chain is configured to implement a particular performance path to maximize performance.
摘要翻译：一种用于通过配置成实现最小化硬件和固件交互的特定性能路径的预定义的硬件操作链来实现存储适配器性能优化的方法和控制器以及提供所述对象控制器电路所在的设计结构。控制器包括多个硬件引擎; 以及数据存储器，被配置为存储选择性地布置在多个预定义链中的一个中的多个控制块。每个预定义链定义一系列操作。每个控制块被设计成控制多个硬件引擎之一的硬件操作。资源句柄结构被配置为基于系统的特定特征来选择预定义的链。每个预定义链被配置为实现特定的性能路径以最大化性能。

18. 发明授权

US08495259B2 Implementing storage adapter performance optimization with hardware chains to select performance path 失效
标题翻译：使用硬件链实现存储适配器性能优化，以选择性能路径
公开(公告)号：US08495259B2
公开(公告)日：2013-07-23
申请号：US13114291
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moerti , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moerti , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F13/28
CPC分类号： G06F3/061 , G06F3/0658 , G06F3/0659 , G06F3/0689 , G06F12/0866
摘要： A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to implement a particular performance path minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a data store configured to store a plurality of control blocks selectively arranged in one of a plurality of predefined chains. Each predefined chain defines a sequence of operations. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A resource handle structure is configured to select a predefined chain based upon a particular characteristic of the system. Each predefined chain is configured to implement a particular performance path to maximize performance.
摘要翻译：一种用于通过配置成实现最小化硬件和固件交互的特定性能路径的预定义的硬件操作链来实现存储适配器性能优化的方法和控制器以及提供所述对象控制器电路所在的设计结构。控制器包括多个硬件引擎; 以及数据存储器，被配置为存储选择性地布置在多个预定义链中的一个中的多个控制块。每个预定义链定义一系列操作。每个控制块被设计成控制多个硬件引擎之一的硬件操作。资源句柄结构被配置为基于系统的特定特征来选择预定义的链。每个预定义链被配置为实现特定的性能路径以最大化性能。

19. 发明授权

US08589598B2 Management of redundant physical data paths in a computing system 失效
标题翻译：管理计算系统中的冗余物理数据路径
公开(公告)号：US08589598B2
公开(公告)日：2013-11-19
申请号：US13363352
申请日：2012-01-31
申请人： Scott A. Bauman , Brian L. Bowles , Anthony P. Vinski , Rick A. Weckwerth
发明人： Scott A. Bauman , Brian L. Bowles , Anthony P. Vinski , Rick A. Weckwerth
IPC分类号： G06F3/00 , G06F15/173
CPC分类号： G06F11/2007
摘要： A redundancy manager manages commands to peripheral devices in a computer system. These peripheral devices have multiple pathways connecting it to the computer system. The redundancy manager determines the number of independent pathways connected to the peripheral device, presents only one logical device to the operating system and any device driver and any other command or device processing logic in the command path before the redundancy manager. For each incoming command, the redundancy manager determines which pathways are properly functioning and selects the best pathway for the command based at least partly upon a penalty model where a path may be temporarily penalized by not including the pathway in the path selection process for a predetermined time. The redundancy manager further reroutes the command to an alternate path and resets the device for an alternate path that is not penalized or has otherwise failed.
摘要翻译：冗余管理器管理命令到计算机系统中的外围设备。这些外围设备具有将其连接到计算机系统的多个路径。冗余管理器确定连接到外围设备的独立路径的数量，在冗余管理器之前，只向操作系统和任何设备驱动程序以及命令路径中的任何其他命令或设备处理逻辑提供一个逻辑设备。对于每个传入命令，冗余管理器至少部分地基于惩罚模型来确定哪些路径正确地起作用并且选择用于命令的最佳路径，其中通过在路径选择过程中不包括用于预定的路径的路径来临时惩罚路径时间。冗余管理器进一步将命令重新路由到备用路径，并将设备重置为不受惩罚或以其他方式失败的备用路径。

20. 发明申请

US20100268857A1 Management of Redundant Physical Data Paths in a Computing System 失效
标题翻译：计算系统中冗余物理数据路径的管理
公开(公告)号：US20100268857A1
公开(公告)日：2010-10-21
申请号：US12426415
申请日：2009-04-20
申请人： Scott A. Bauman , Brian L. Bowles , Anthony P. Vinski , Rick A. Weckwerth
发明人： Scott A. Bauman , Brian L. Bowles , Anthony P. Vinski , Rick A. Weckwerth
IPC分类号： G06F13/12 , G06F13/00
CPC分类号： G06F11/2007 , G06F11/0745 , G06F11/0781
摘要： A redundancy manager manages commands to peripheral devices in a computer system. These peripheral devices have multiple pathways connecting it to the computer system. The redundancy manager determines the number of independent pathways connected to the peripheral device, presents only one logical device to the operating system and any device driver and any other command or device processing logic in the command path before the redundancy manager. For each incoming command, the redundancy manager determines which pathways are properly functioning and selects the best pathway for the command based at least partly upon a penalty model where a path may be temporarily penalized by not including the pathway in the path selection process for a predetermined time. The redundancy manager further reroutes the command to an alternate path and resets the device for an alternate path that is not penalized or has otherwise failed.
摘要翻译：冗余管理器管理命令到计算机系统中的外围设备。这些外围设备具有将其连接到计算机系统的多个路径。冗余管理器确定连接到外围设备的独立路径的数量，在冗余管理器之前，只向操作系统和任何设备驱动程序以及命令路径中的任何其他命令或设备处理逻辑提供一个逻辑设备。对于每个传入命令，冗余管理器至少部分地基于惩罚模型来确定哪些路径正确地起作用并且选择用于命令的最佳路径，其中通过在路径选择过程中不包括用于预定的路径的路径来临时惩罚路径时间。冗余管理器进一步将命令重新路由到备用路径，并将设备重置为不受惩罚或以其他方式失败的备用路径。

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