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    • 11. 发明授权
    • Method and system for accessing data from a multi-head data processing
system utilizing a transducer head switching table
    • 用于使用换能器头切换台从多头数据处理系统访问数据的方法和系统
    • US5426758A
    • 1995-06-20
    • US949672
    • 1992-09-23
    • Susan K. CandelariaDean L. HansonRobert L. KwokKenneth W. LaneDonald M. NordahlMark A. ReidWilliam G. Sherman, II
    • Susan K. CandelariaDean L. HansonRobert L. KwokKenneth W. LaneDonald M. NordahlMark A. ReidWilliam G. Sherman, II
    • G06F3/06G11B19/00G11B19/02G11B27/00G06F12/00G11B5/55
    • G06F3/0601G11B19/00G11B19/02G11B27/002G06F2003/0692G11B2220/20
    • A method and system for enhancing the efficiency of data accessing within a storage subsystem which is coupled to a host system via a storage subsystem controller and a data channel. The storage subsystem controller preferably includes a tracked cyclic storage device which has multiple disks which are rotatable about a single spindle. Recording tracks within each disk are then accessed utilizing multiple switchable transducer heads. A signal transmitted from the host system is utilized to define a sequence in which a group of recording tracks are to be accessed. That signal is then utilized to create a transducer head switching table within the storage subsystem controller which lists each recording track to be accessed and an associated control parameter for selecting a particular transducer head to be utilized to access a subsequent recording track. Each time the end of an accessed recording track is encountered, the transducer head switching table is accessed and the control parameter associated with that track is accessed and coupled to the tracked cyclic storage device transducer head switch in order to select a subsequent recording track for access. In this manner, a plurality of tracks may be accessed in any desired order. A pointer is established into the transducer head switching table at the listing of an initially accessed recording track and access may be terminated when that pointer is encountered.
    • 一种用于增强在经由存储子系统控制器和数据信道耦合到主机系统的存储子系统内的数据访问的效率的方法和系统。 存储子系统控制器优选地包括跟踪的循环存储设备,其具有可围绕单个主轴旋转的多个盘。 然后使用多个可切换的换能器头访问每个磁盘内的记录磁道。 使用从主机系统发送的信号来定义要访问一组记录磁道的序列。 该信号然后用于在存储子系统控制器内创建换能器头切换台,其中列出了要被访问的每个记录轨道,以及相关联的控制参数,用于选择要用于访问后续记录轨道的特定换能器头。 每次遇到访问的记录轨道的结束时,传感器头切换台被访问,并且与该轨道相关联的控制参数被访问并耦合到被跟踪的循环存储设备换能器头切换器,以便选择随后的记录轨道进行访问 。 以这种方式,可以以任何期望的顺序访问多个轨道。 在最初访问的记录轨道的列表中,将指针建立到换能器头切换台中,并且当遇到该指针时可以终止访问。
    • 13. 发明授权
    • Apparatus, system, and method for device level enablement of a communications protocol
    • 用于通信协议的设备级启用的装置,系统和方法
    • US08819218B2
    • 2014-08-26
    • US12565995
    • 2009-09-24
    • Susan K. CandelariaRoger G. HathornMatthew J. KalosBeth Peterson
    • Susan K. CandelariaRoger G. HathornMatthew J. KalosBeth Peterson
    • G06F15/173G06F15/16G06F11/30G21C17/00H04L1/24H04L12/26H04L29/06
    • H04L1/244H04L29/06537H04L41/0803H04L43/50H04L69/18H04L69/24
    • An apparatus, system, and method are disclosed for device level enablement of a communications protocol. An adapter compatibility module determines an adapter compatibility status for a plurality of host adapters. A positive adapter compatibility status indicates that each host adapter in the plurality of host adapters is compatible with a communications protocol. A processor compatibility module determines a processor compatibility status for one or more processors. The one or more processors coordinate data transfers to and from the plurality of host adapters. A positive processor compatibility status indicates that each of the one or more processors is compatible with the communications protocol. A compatibility summary module determines a compatibility summary for the plurality of host adapters and the one or more processors. The compatibility summary indicates a positive compatibility relative to the communications protocol in response to a positive processor compatibility status and a positive adapter compatibility status.
    • 公开了一种用于通信协议的设备级实现的装置,系统和方法。 适配器兼容性模块确定多个主机适配器的适配器兼容性状态。 正适配器兼容性状态表示多个主机适配器中的每个主机适配器与通信协议兼容。 处理器兼容性模块确定一个或多个处理器的处理器兼容性状态。 一个或多个处理器协调到和从多个主机适配器的数据传输。 正处理器兼容性状态表示一个或多个处理器中的每一个与通信协议兼容。 兼容性摘要模块确定多个主机适配器和一个或多个处理器的兼容性摘要。 响应于正处理器兼容性状态和正适配器兼容性状态,兼容性摘要指示相对于通信协议的正确兼容性。
    • 14. 发明申请
    • APPARATUS, SYSTEM, AND METHOD FOR DEVICE LEVEL ENABLEMENT OF A COMMUNICATIONS PROTOCOL
    • 用于设备级别启动通信协议的装置,系统和方法
    • US20110072153A1
    • 2011-03-24
    • US12565995
    • 2009-09-24
    • Susan K. CandelariaRoger G. HathornMatthew J. KalosBeth A. Peterson
    • Susan K. CandelariaRoger G. HathornMatthew J. KalosBeth A. Peterson
    • G06F15/16
    • H04L1/244H04L29/06537H04L41/0803H04L43/50H04L69/18H04L69/24
    • An apparatus, system, and method are disclosed for device level enablement of a communications protocol. An adapter compatibility module determines an adapter compatibility status for a plurality of host adapters. A positive adapter compatibility status indicates that each host adapter in the plurality of host adapters is compatible with a communications protocol. A processor compatibility module determines a processor compatibility status for one or more processors. The one or more processors coordinate data transfers to and from the plurality of host adapters. A positive processor compatibility status indicates that each of the one or more processors is compatible with the communications protocol. A compatibility summary module determines a compatibility summary for the plurality of host adapters and the one or more processors. The compatibility summary indicates a positive compatibility relative to the communications protocol in response to a positive processor compatibility status and a positive adapter compatibility status.
    • 公开了一种用于通信协议的设备级实现的装置,系统和方法。 适配器兼容性模块确定多个主机适配器的适配器兼容性状态。 正适配器兼容性状态表示多个主机适配器中的每个主机适配器与通信协议兼容。 处理器兼容性模块确定一个或多个处理器的处理器兼容性状态。 一个或多个处理器协调到和从多个主机适配器的数据传输。 正处理器兼容性状态表示一个或多个处理器中的每一个与通信协议兼容。 兼容性摘要模块确定多个主机适配器和一个或多个处理器的兼容性摘要。 响应于正处理器兼容性状态和正适配器兼容性状态,兼容性摘要指示相对于通信协议的正确兼容性。