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11. 发明授权

US09186127B2 Ultrasonic diagnosis apparatus and method of controlling output of ultrasonic diagnosis apparatus 有权
标题翻译：超声波诊断装置及超声波诊断装置的输出控制方法
公开(公告)号：US09186127B2
公开(公告)日：2015-11-17
申请号：US13108427
申请日：2011-05-16
申请人： Sandstrom Kurt , Dae Young Kim , Soo Hwan Shin , Tae-Yun Kim
发明人： Sandstrom Kurt , Dae Young Kim , Soo Hwan Shin , Tae-Yun Kim
IPC分类号： A61B8/00 , A61B5/00 , A61B17/00 , G01S7/52
CPC分类号： A61B8/54 , A61B8/4444 , A61B8/465 , A61B8/467 , A61B8/56 , A61B8/585 , G01S7/5205
摘要： Provided is a method of controlling voltage levels of overall outputs in a combinational mode, in an ultrasonic diagnosis apparatus that may operate in the combinational mode. A judging unit of the ultrasonic diagnosis apparatus may judge whether at least a part of individual modes included in the combinational mode exceeds a threshold determined by safety standards, in accordance with an inputted overall output voltage level control command. When it is judged that at least the part of the individual modes exceeds the threshold determined by the safety standards, an output control unit may maintain an individual output with respect to the at least the part, among the voltage levels that may be outputted from a transducer, to be below the threshold, so that the individual output may be below the standards in accordance with the overall output control command.
摘要翻译：提供了一种在组合模式中可以操作的超声波诊断装置中控制组合模式的总输出的电压电平的方法。超声波诊断装置的判断单元可以根据输入的总输出电压电平控制指令来判断组合模式中包括的各个模式的至少一部分是否超过由安全标准确定的阈值。当判定至少部分单个模式超过由安全标准确定的阈值时，输出控制单元可以相对于至少该部分保持可输出的电压中的至少一部分的单独输出传感器低于阈值，使得单个输出可以根据总输出控制命令低于标准。

12. 外观设计

USD687831S1 Notebook computer 有权
公开(公告)号：USD687831S1
公开(公告)日：2013-08-13
申请号：US29422779
申请日：2012-05-23
申请人： Tae-Yun Kim
设计人： Tae-Yun Kim

13. 发明授权

US08143927B2 Pulse control device 有权
标题翻译：脉冲控制装置
公开(公告)号：US08143927B2
公开(公告)日：2012-03-27
申请号：US13091544
申请日：2011-04-21
申请人： Kyoung-Nam Kim , Tae-Yun Kim
发明人： Kyoung-Nam Kim , Tae-Yun Kim
IPC分类号： H03K5/04
CPC分类号： G06F1/04 , H03K5/1565 , H03K2005/00091
摘要： A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.
摘要翻译：维持脉冲控制装置，其具有对应于过程或温度变化的恒定脉冲宽度。所述脉冲控制装置包括用于选择性地输出延迟增加信号和延迟减小信号的熔丝，所述延迟增加信号和延迟减小信号基于其上编程关于过程改变的信息的熔丝的切割或非切割状态具有不同的状态，以及脉冲发生器，其具有预定的时间延迟的多个延迟单元，用于根据所述延迟增加信号和所述延迟减小信号选择性地增加或减少所述多个延迟单元的数量，以产生具有对应于所述数量的脉冲宽度的内部时钟的延迟细胞增加或减少。

14. 发明授权

US07622973B2 Pulse control device 有权
标题翻译：脉冲控制装置
公开(公告)号：US07622973B2
公开(公告)日：2009-11-24
申请号：US11477591
申请日：2006-06-30
申请人： Kyoung-Nam Kim , Tae-Yun Kim
发明人： Kyoung-Nam Kim , Tae-Yun Kim
IPC分类号： H03K5/04
CPC分类号： G06F1/04 , H03K5/1565 , H03K2005/00091
摘要： Provided is a pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.
摘要翻译：提供了一种脉冲控制装置，其具有对应于过程或温度变化的恒定脉冲宽度。所述脉冲控制装置包括用于选择性地输出延迟增加信号和延迟减小信号的熔丝，所述延迟增加信号和延迟减小信号基于其上编程关于过程改变的信息的熔丝的切割或非切割状态具有不同的状态，以及脉冲发生器，其具有预定的时间延迟的多个延迟单元，用于根据所述延迟增加信号和所述延迟减小信号选择性地增加或减少所述多个延迟单元的数量，以产生具有对应于所述数量的脉冲宽度的内部时钟的延迟细胞增加或减少。

15. 发明授权

US07560978B2 Internal voltage detection circuit 有权
标题翻译：内部电压检测电路
公开(公告)号：US07560978B2
公开(公告)日：2009-07-14
申请号：US11806558
申请日：2007-06-01
申请人： Sang-Jin Byeon , Tae-Yun Kim , Jun-Gi Choi
发明人： Sang-Jin Byeon , Tae-Yun Kim , Jun-Gi Choi
IPC分类号： G05F1/10
CPC分类号： G05F1/465
摘要： An internal voltage generator for use in a semiconductor memory device includes a first voltage detection unit, a second voltage detection unit, a detection signal generation unit, and an internal voltage generation unit. The first voltage detection unit detects a voltage level of an internal voltage changing linearly depending on a temperature variation to output a first detection signal. The second voltage detection unit detects the voltage level having a constant value without concerning the temperature variation to output a second detection signal. The detection signal output unit combines the first and the second detection signal to generate a combined detection signal for detecting the voltage level linearly varying according to the temperature variation in a first range of temperature and detecting the voltage level having the constant value in a second range of temperature.
摘要翻译：用于半导体存储器件的内部电压发生器包括第一电压检测单元，第二电压检测单元，检测信号生成单元和内部电压产生单元。第一电压检测单元检测根据温度变化线性变化的内部电压的电压电平，以输出第一检测信号。第二电压检测单元检测具有恒定值的电压电平而不涉及温度变化以输出第二检测信号。检测信号输出单元组合第一和第二检测信号以产生组合检测信号，用于根据第一温度范围内的温度变化检测线性变化的电压电平，并检测具有第二范围中的常数值的电压电平的温度。

16. 发明申请

US20070279123A1 Internal voltage detection circuit 有权
标题翻译：内部电压检测电路
公开(公告)号：US20070279123A1
公开(公告)日：2007-12-06
申请号：US11806558
申请日：2007-06-01
申请人： Sang-Jin Byeon , Tae-Yun Kim , Jun-Gi Choi
发明人： Sang-Jin Byeon , Tae-Yun Kim , Jun-Gi Choi
IPC分类号： G05F1/10
CPC分类号： G05F1/465
摘要： An internal voltage generator for use in a semiconductor memory device includes a first voltage detection unit, a second voltage detection unit, a detection signal generation unit, and an internal voltage generation unit. The first voltage detection unit detects a voltage level of an internal voltage changing linearly depending on a temperature variation to output a first detection signal. The second voltage detection unit detects the voltage level having a constant value without concerning the temperature variation to output a second detection signal. The detection signal output unit combines the first and the second detection signal to generate a combined detection signal for detecting the voltage level linearly varying according to the temperature variation in a first range of temperature and detecting the voltage level having the constant value in a second range of temperature.
摘要翻译：用于半导体存储器件的内部电压发生器包括第一电压检测单元，第二电压检测单元，检测信号生成单元和内部电压产生单元。第一电压检测单元检测根据温度变化线性变化的内部电压的电压电平，以输出第一检测信号。第二电压检测单元检测具有恒定值的电压电平而不涉及温度变化以输出第二检测信号。检测信号输出单元组合第一和第二检测信号以产生组合检测信号，用于根据第一温度范围内的温度变化检测线性变化的电压电平，并检测具有第二范围中的常数值的电压电平的温度。

17. 发明授权

US06430100B2 Redundancy circuitry for repairing defects in packaged memory having registers 失效
标题翻译：用于修复具有寄存器的封装存储器中的缺陷的冗余电路
公开(公告)号：US06430100B2
公开(公告)日：2002-08-06
申请号：US09734581
申请日：2000-12-13
申请人： Tae-Yun Kim
发明人： Tae-Yun Kim
IPC分类号： G11C700
CPC分类号： G11C29/824
摘要： A redundancy circuitry is used in a memory device for repairing defects in a packaged memory having registers by using antifuse. The redundancy circuitry includes: an anticell for storing data to be replaced; a temporary anticell for storing the data temporarily; a row and a column antifuse composed of antifuse and anti enable fuse corresponding to a row and column address, respectively; an antifuse controller for controlling the programming of the antifuse; a voltage supplier for supplying a voltage to program the antifuse; a row and a column comparators for comparing the programmed row and column antifuses and the external input address, respectively; an anti-controller for controlling to provide data from the anticell on a read operation and to temporarily store the external data to the temporary anticell on a write operation based on the comparison signals; a restore controller for, based on the row address on a restore operation, transferring the external data identical to the programmed fuse address to the anticell; and a channel selection memory for storing the channel address for pre-fetch and restore operations provided during read and write operations.
摘要翻译：冗余电路用于存储器件中，用于通过使用反熔丝修复具有寄存器的封装存储器中的缺陷。冗余电路包括：用于存储要被替换的数据的解码器; 用于临时存储数据的临时anticell; 分别由对应于行和列地址的反熔丝和反使能熔丝组成的一列和一列反熔丝; 用于控制反熔丝编程的反熔丝控制器; 用于提供电压来编程反熔丝的电压供应器; 用于分别比较编程的行和列反相变换和外部输入地址的行和列比较器; 一个反控制器，用于控制在读取操作时提供来自反码器的数据，并且在基于比较信号的写入操作中将外部数据临时存储到临时防变频器; 恢复控制器，用于基于还原操作上的行地址将与编程的熔丝地址相同的外部数据传送到该抗蚀剂; 以及用于存储在读取和写入操作期间提供的用于预取和恢复操作的通道地址的通道选择存储器。

18. 发明申请

US20110193604A1 PULSE CONTROL DEVICE 有权
标题翻译：脉冲控制装置
公开(公告)号：US20110193604A1
公开(公告)日：2011-08-11
申请号：US13091544
申请日：2011-04-21
申请人： Kyoung-Nam KIM , Tae-Yun Kim
发明人： Kyoung-Nam KIM , Tae-Yun Kim
IPC分类号： H03K5/04
CPC分类号： G06F1/04 , H03K5/1565 , H03K2005/00091
摘要： A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.
摘要翻译：维持脉冲控制装置，其具有对应于过程或温度变化的恒定脉冲宽度。所述脉冲控制装置包括用于选择性地输出延迟增加信号和延迟减小信号的熔丝，所述延迟增加信号和延迟减小信号基于其上编程关于过程改变的信息的熔丝的切割或非切割状态具有不同的状态，以及脉冲发生器，其具有预定的时间延迟的多个延迟单元，用于根据所述延迟增加信号和所述延迟减小信号选择性地增加或减少所述多个延迟单元的数量，以产生具有对应于所述数量的脉冲宽度的内部时钟的延迟细胞增加或减少。

19. 发明授权

US07629822B2 Delay locked loop in semiconductor memory device and method for generating divided clock therein 失效
标题翻译：半导体存储器件中的延迟锁定环和其中产生分频时钟的方法
公开(公告)号：US07629822B2
公开(公告)日：2009-12-08
申请号：US12078095
申请日：2008-03-27
申请人： Kyoung-Nam Kim , Tae-Yun Kim
发明人： Kyoung-Nam Kim , Tae-Yun Kim
IPC分类号： H03L7/06
CPC分类号： G11C7/1072 , G11C7/222
摘要： Provided are a delay locked loop (DLL) and a method for generating a divided clock therein. In the DLL, a width of a reference frequency for phase comparison can be changed depending on a magnitude of an operating frequency. In the DLL, a clock buffer receives a clock equal to an external clock and generates an internal clock. An enable clock generator generates a 1-period enable clock or a 2-period enable clock using a command signal generated for performing a predefined operation. The command signal is generated according to an address command signal inputted from an exterior. A clock divider divides the internal clock to generate a divided clock. The divided clock is controlled by the 1-period enable clock or the 2-period enable clock, such that the divided clock is made to be a 1-period based dividing clock or a 2-period based dividing clock.
摘要翻译：提供了一种延迟锁定环（DLL）和用于在其中产生分频时钟的方法。在DLL中，用于相位比较的参考频率的宽度可以根据工作频率的大小而改变。在DLL中，时钟缓冲器接收等于外部时钟的时钟并产生内部时钟。使能时钟发生器使用为执行预定义的操作生成的命令信号生成1周期使能时钟或2周期使能时钟。根据从外部输入的地址指令信号生成指令信号。时钟分频器分隔内部时钟以产生分频时钟。分频时钟由1周期使能时钟或2周期使能时钟控制，使得分频时钟为1周期分频时钟或2周期分频时钟。

20. 发明授权

US07368964B2 Delay locked loop in semiconductor memory device and method for generating divided clock therein 失效
标题翻译：半导体存储器件中的延迟锁定环和其中产生分频时钟的方法
公开(公告)号：US07368964B2
公开(公告)日：2008-05-06
申请号：US11320847
申请日：2005-12-30
申请人： Kyoung-Nam Kim , Tae-Yun Kim
发明人： Kyoung-Nam Kim , Tae-Yun Kim
IPC分类号： H03L7/06
CPC分类号： G11C7/1072 , G11C7/222
摘要： Provided are a delay locked loop (DLL) and a method for generating a divided clock therein. In the DLL, a width of a reference frequency for phase comparison can be changed depending on a magnitude of an operating frequency. In the DLL, a clock buffer receives a clock equal to an external clock and generates an internal clock. An enable clock generator generates a 1-period enable clock or a 2-period enable clock using a command signal generated for performing a predefined operation. The command signal is generated according to an address command signal inputted from an exterior. A clock divider divides the internal clock to generate a divided clock. The divided clock is controlled by the 1-period enable clock or the 2-period enable clock, such that the divided clock is made to be a 1-period based dividing clock or a 2-period based dividing clock.
摘要翻译：提供了一种延迟锁定环（DLL）和用于在其中产生分频时钟的方法。在DLL中，用于相位比较的参考频率的宽度可以根据工作频率的大小而改变。在DLL中，时钟缓冲器接收等于外部时钟的时钟并产生内部时钟。使能时钟发生器使用为执行预定义的操作生成的命令信号生成1周期使能时钟或2周期使能时钟。根据从外部输入的地址指令信号生成指令信号。时钟分频器分隔内部时钟以产生分频时钟。分频时钟由1周期使能时钟或2周期使能时钟控制，使得分频时钟为1周期分频时钟或2周期分频时钟。

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