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11. 发明申请

US20080272398A1 CONDUCTIVE SPACERS FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING 有权
标题翻译：用于半导体器件的导电间隔件和形成方法
公开(公告)号：US20080272398A1
公开(公告)日：2008-11-06
申请号：US11848597
申请日：2007-08-31
申请人： Gary Bela Bronner , David Michael Fried , Jeffrey Peter Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Y. Sardesai
发明人： Gary Bela Bronner , David Michael Fried , Jeffrey Peter Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Y. Sardesai
IPC分类号： H01L29/00
CPC分类号： H01L21/26586 , H01L21/28518 , H01L21/76895 , H01L21/823468 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.
摘要翻译：一种在半导体器件上形成导电间隔物的方法。该方法包括在半导体器件上沉积多晶硅层，在半导体器件的晶体管区域的第一侧上选择性地将多晶硅层中的掺杂剂离子注入以限定导电间隔区，以及除去导电间隔区之外的多晶硅层。任选地，可以在导电间隔物区域上进行硅化处理，使得导电间隔物由金属硅化物构成。

12. 发明授权

US08741718B2 Local interconnects compatible with replacement gate structures 有权
标题翻译：局部互连与替换门结构兼容
公开(公告)号：US08741718B2
公开(公告)日：2014-06-03
申请号：US13351294
申请日：2012-01-17
申请人： Viraj Y. Sardesai
发明人： Viraj Y. Sardesai
IPC分类号： H01L21/336
CPC分类号： H01L23/481 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L2924/0002 , H01L2924/00
摘要： After forming replacement gate structures that are embedded in a planarized dielectric layer on a semiconductor substrate, a contact-level dielectric layer is deposited over a planar surface of the planarized dielectric layer and the replacement gate structures. Substrate contact via holes are formed through the contact-level dielectric layer and the planarized dielectric layer, and metal semiconductor alloy portions are formed on exposed semiconductor materials. Gate contact via holes are subsequently formed through the contact-level dielectric layer. The substrate contact via holes and the gate contact via holes are simultaneously filled with a conductive material to form substrate contact structures and gate contact structures. The substrate contact structures and gate contact structures can be employed to provide local interconnect structures that provide electrical connections between two components that are laterally spaced on the semiconductor substrate.
摘要翻译：在形成嵌入在半导体衬底上的平坦化电介质层中的替代栅极结构之后，在平坦化介电层和替换栅极结构的平坦表面上沉积接触电介质层。通过接触电介质层和平坦化介电层形成基板接触孔，并且在暴露的半导体材料上形成金属半导体合金部分。随后通过接触电介质层形成栅极接触通孔。衬底接触通孔和栅极接触通孔同时用导电材料填充以形成衬底接触结构和栅极接触结构。衬底接触结构和栅极接触结构可用于提供局部互连结构，其提供在半导体衬底上横向间隔开的两个部件之间的电连接。

13. 发明授权

US08603915B2 Multi-stage silicidation process 有权
标题翻译：多级硅化工艺
公开(公告)号：US08603915B2
公开(公告)日：2013-12-10
申请号：US13305122
申请日：2011-11-28
申请人： Emre Alptekin , Ahmet S. Ozcan , Viraj Y. Sardesai , Cung D. Tran
发明人： Emre Alptekin , Ahmet S. Ozcan , Viraj Y. Sardesai , Cung D. Tran
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/76814 , H01L21/76816 , H01L21/76897
摘要： A multi-stage silicidation process is described wherein a dielectric etch to expose contact regions is timed to be optimal for a highest of the contact regions. After exposing the highest of the contact regions, a silicide is formed on the exposed contact region and the dielectric is re-etched, selective to the formed silicide, to expose another contact region, lower than the highest of the contact regions, without recessing the highest of the contact regions. The process then forms a silicide on the lower contact region. The process may continue to varying depths. Each subsequent etch is performed without the use of additional masking steps. By manipulating diffusive properties of existing silicides and deposited metals, the silicides formed on contact regions with differing depths/height may comprise different compositions and be optimized for different polarity devices such as nFET and pFET devices.
摘要翻译：描述了一种多级硅化工艺，其中用于暴露接触区域的电介质蚀刻被定时以对于最高的接触区域是最佳的。在暴露最高的接触区域之后，在暴露的接触区域上形成硅化物，并且对所形成的硅化物进行选择性地再次蚀刻电介质以暴露低于最高接触区域的另一个接触区域，而不会使最高的接触区域。然后，该过程在下接触区域上形成硅化物。该过程可能继续变化深度。在不使用附加掩蔽步骤的情况下执行每个后续蚀刻。通过操纵现有硅化物和沉积金属的扩散性能，形成在具有不同深度/高度的接触区域上的硅化物可以包含不同的组成，并针对不同的极性器件如nFET和pFET器件进行优化。

14. 发明申请

US20130137260A1 MULTI-STAGE SILICIDATION PROCESS 有权
标题翻译：多级硅化工艺
公开(公告)号：US20130137260A1
公开(公告)日：2013-05-30
申请号：US13305122
申请日：2011-11-28
申请人： Emre Alptekin , Ahmet S. Ozcan , Viraj Y. Sardesai , Cung D. Tran
发明人： Emre Alptekin , Ahmet S. Ozcan , Viraj Y. Sardesai , Cung D. Tran
IPC分类号： H01L21/3205
CPC分类号： H01L21/28518 , H01L21/76814 , H01L21/76816 , H01L21/76897
摘要： A multi-stage silicidation process is described wherein a dielectric etch to expose contact regions is timed to be optimal for a highest of the contact regions. After exposing the highest of the contact regions, a silicide is formed on the exposed contact region and the dielectric is re-etched, selective to the formed silicide, to expose another contact region, lower than the highest of the contact regions, without recessing the highest of the contact regions. The process then forms a silicide on the lower contact region. The process may continue to varying depths. Each subsequent etch is performed without the use of additional masking steps. By manipulating diffusive properties of existing silicides and deposited metals, the silicides formed on contact regions with differing depths/height may comprise different compositions and be optimized for different polarity devices such as nFET and pFET devices.
摘要翻译：描述了一种多级硅化工艺，其中用于暴露接触区域的电介质蚀刻被定时以对于最高的接触区域是最佳的。在暴露最高的接触区域之后，在暴露的接触区域上形成硅化物，并且对所形成的硅化物进行选择性地再次蚀刻电介质以暴露低于最高接触区域的另一个接触区域，而不会使最高的接触区域。然后，该过程在下接触区域上形成硅化物。该过程可能继续变化深度。在不使用附加掩蔽步骤的情况下执行每个后续蚀刻。通过操纵现有硅化物和沉积金属的扩散性能，形成在具有不同深度/高度的接触区域上的硅化物可以包含不同的组成，并针对不同的极性器件如nFET和pFET器件进行优化。

15. 发明申请

US20120306093A1 CONVERTING METAL MASK TO METAL-OXIDE ETCH STOP LAYER AND RELATED SEMICONDUCTOR STRUCTURE 有权
标题翻译：将金属掩模转换为金属氧化物蚀刻停止层和相关半导体结构
公开(公告)号：US20120306093A1
公开(公告)日：2012-12-06
申请号：US13151646
申请日：2011-06-02
申请人： Brett H. Engel , Ying Li , Viraj Y. Sardesai , Richard S. Wise
发明人： Brett H. Engel , Ying Li , Viraj Y. Sardesai , Richard S. Wise
IPC分类号： H01L21/283 , H01L23/48 , B82Y40/00 , B82Y99/00
CPC分类号： H01L21/31144 , H01L21/02178 , H01L21/02244 , H01L21/02252 , H01L21/76804 , H01L21/7681 , H01L21/76829
摘要： A method includes providing a semiconductor structure including a plurality of devices; depositing a nitride cap over the semiconductor structure; forming an aluminum mask over the nitride cap, the aluminum mask including a plurality of first openings; converting the aluminum mask to an aluminum oxide etch stop layer; and performing middle-of-line fabrication processing, leaving the aluminum oxide etch stop layer in place. A semiconductor structure includes a plurality of devices on a substrate; a nitride cap over the plurality of devices; an aluminum oxide etch stop layer over the nitride cap; an inter-level dielectric (ILD) over the aluminum oxide etch stop layer; and a plurality of contacts extending through the ILD, the aluminum oxide etch stop layer and the nitride cap to the plurality of devices.
摘要翻译：一种方法包括提供包括多个装置的半导体结构; 在所述半导体结构上沉积氮化物盖; 在所述氮化物盖上形成铝掩模，所述铝掩模包括多个第一开口; 将铝掩模转变成氧化铝蚀刻停止层; 并执行中间线制造处理，将氧化铝蚀刻停止层留在原位。半导体结构在基板上包括多个器件; 多个装置上的氮化物盖; 在氮化物盖上方的氧化铝蚀刻停止层; 氧化铝蚀刻停止层上的层间电介质（ILD）; 以及穿过ILD延伸的多个触点，氧化铝蚀刻停止层和氮化物帽到多个器件。

16. 发明申请

US20130181292A1 LOCAL INTERCONNECTS COMPATIBLE WITH REPLACEMENT GATE STRUCTURES 有权
标题翻译：本地互连与替代门结构兼容
公开(公告)号：US20130181292A1
公开(公告)日：2013-07-18
申请号：US13351294
申请日：2012-01-17
申请人： Viraj Y. Sardesai
发明人： Viraj Y. Sardesai
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L23/481 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L2924/0002 , H01L2924/00
摘要： After forming replacement gate structures that are embedded in a planarized dielectric layer on a semiconductor substrate, a contact-level dielectric layer is deposited over a planar surface of the planarized dielectric layer and the replacement gate structures. Substrate contact via holes are formed through the contact-level dielectric layer and the planarized dielectric layer, and metal semiconductor alloy portions are formed on exposed semiconductor materials. Gate contact via holes are subsequently formed through the contact-level dielectric layer. The substrate contact via holes and the gate contact via holes are simultaneously filled with a conductive material to form substrate contact structures and gate contact structures. The substrate contact structures and gate contact structures can be employed to provide local interconnect structures that provide electrical connections between two components that are laterally spaced on the semiconductor substrate.
摘要翻译：在形成嵌入在半导体衬底上的平坦化电介质层中的替代栅极结构之后，在平坦化介电层和替换栅极结构的平坦表面上沉积接触电介质层。通过接触电介质层和平坦化介电层形成基板接触孔，并且在暴露的半导体材料上形成金属半导体合金部分。随后通过接触电介质层形成栅极接触通孔。衬底接触通孔和栅极接触通孔同时用导电材料填充以形成衬底接触结构和栅极接触结构。衬底接触结构和栅极接触结构可用于提供局部互连结构，其提供在半导体衬底上横向间隔开的两个部件之间的电连接。

17. 发明授权

US08435891B2 Converting metal mask to metal-oxide etch stop layer and related semiconductor structure 有权
标题翻译：将金属掩模转换为金属氧化物蚀刻停止层和相关的半导体结构
公开(公告)号：US08435891B2
公开(公告)日：2013-05-07
申请号：US13151646
申请日：2011-06-02
申请人： Brett H. Engel , Ying Li , Viraj Y. Sardesai , Richard S. Wise
发明人： Brett H. Engel , Ying Li , Viraj Y. Sardesai , Richard S. Wise
IPC分类号： H01L21/283
CPC分类号： H01L21/31144 , H01L21/02178 , H01L21/02244 , H01L21/02252 , H01L21/76804 , H01L21/7681 , H01L21/76829
摘要： A method includes providing a semiconductor structure including a plurality of devices; depositing a nitride cap over the semiconductor structure; forming an aluminum mask over the nitride cap, the aluminum mask including a plurality of first openings; converting the aluminum mask to an aluminum oxide etch stop layer; and performing middle-of-line fabrication processing, leaving the aluminum oxide etch stop layer in place. A semiconductor structure includes a plurality of devices on a substrate; a nitride cap over the plurality of devices; an aluminum oxide etch stop layer over the nitride cap; an inter-level dielectric (ILD) over the aluminum oxide etch stop layer; and a plurality of contacts extending through the ILD, the aluminum oxide etch stop layer and the nitride cap to the plurality of devices.
摘要翻译：一种方法包括提供包括多个装置的半导体结构; 在所述半导体结构上沉积氮化物盖; 在所述氮化物盖上形成铝掩模，所述铝掩模包括多个第一开口; 将铝掩模转变成氧化铝蚀刻停止层; 并执行中间线制造处理，将氧化铝蚀刻停止层留在原位。半导体结构在基板上包括多个器件; 多个装置上的氮化物盖; 在氮化物盖上方的氧化铝蚀刻停止层; 氧化铝蚀刻停止层上的层间电介质（ILD）; 以及穿过ILD延伸的多个触点，氧化铝蚀刻停止层和氮化物帽到多个器件。

18. 发明授权

US06740568B2 Method to enhance epitaxial regrowth in amorphous silicon contacts 有权
标题翻译：增强非晶硅接触中的外延再生长的方法
公开(公告)号：US06740568B2
公开(公告)日：2004-05-25
申请号：US10206875
申请日：2002-07-29
申请人： Yun Yu Wang , Johnathan Faltermeier , Colleen M. Snavely , Michael Maldei , Michael M. Iwatake , David M. Dobuzinsky , Ravikumar Ramachandran , Viraj Y. Sardesai , Philip L. Flaitz , Lisa Y. Ninomiya
发明人： Yun Yu Wang , Johnathan Faltermeier , Colleen M. Snavely , Michael Maldei , Michael M. Iwatake , David M. Dobuzinsky , Ravikumar Ramachandran , Viraj Y. Sardesai , Philip L. Flaitz , Lisa Y. Ninomiya
IPC分类号： H01L2136
CPC分类号： H01L21/02667 , H01L21/02046 , H01L21/02532 , H01L21/2022 , H01L21/28525 , H01L27/10873
摘要： In a method of forming a contact, a liner reactive ion etch is affected on a substrate to remove silicon nitride and silicon oxide. An oxygen plasma ex-situ clean, a Huang AB clean, and a dilute hydrofluric acid (DHF) clean are affected. Amorphous silicon is deposited and an anneal is performed to regrow and recrystallize amorphous silicon.
摘要翻译：在形成接触的方法中，在衬底上影响衬里反应离子蚀刻以去除氮化硅和氧化硅。氧等离子体原位清洗，黄AB清洁剂和稀释的氢氟酸（DHF）清洁剂都受到影响。沉积非晶硅并进行退火以再结晶并重结晶非晶硅。

19. 发明授权

US6117778A Semiconductor wafer edge bead removal method and tool 失效
公开(公告)号：US6117778A
公开(公告)日：2000-09-12
申请号：US021762
申请日：1998-02-11
申请人： Bradley P. Jones , Viraj Y. Sardesai
发明人： Bradley P. Jones , Viraj Y. Sardesai
IPC分类号： H01L21/00 , H01L21/3105 , H01L21/302
CPC分类号： H01L21/6708 , H01L21/31053
摘要： A method for planarizing a dielectric layer on a semiconductor wafer is provided. In one aspect, the wafer is coated with a resist and the resist selectively removed forming an uncoated peripheral portion of the wafer. The partially coated wafer is then exposed to an etchant such as RIE to etch the dielectric material not covered by the resist and forming a profiled dielectric layer having a thinner peripheral dielectric portion and a remaining thicker original dielectric central portion. The profiled wafer is then planarized using CMP. The dielectric layer is typically SiO.sub.2, PSG, BSP, or BPSG. In another method and apparatus of the invention, a dielectric coated wafer is secured to a rotating turntable and a liquid etchant sprayed at the periphery of the wafer from a distribution conduit to etch and remove dielectric from a circumferential edge of the wafer forming a profiled dielectric layer as above which is then planarized by CMP. In another aspect of the invention, a CMP polished semiconductor wafer having an edge bead is planarized by polishing only the edge bead of the dielectric layer using a special polishing tool or a CMP apparatus to remove the edge bead from the dielectric layer. Planarized semiconductor wafers made using the method and apparatus of the invention are also provided.

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