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11. 发明授权

US08463832B1 Digital signal processing block architecture for programmable logic device 有权
标题翻译：用于可编程逻辑器件的数字信号处理块架构
公开(公告)号：US08463832B1
公开(公告)日：2013-06-11
申请号：US12146042
申请日：2008-06-25
申请人： Asher Hazanchuk , Ian Ing , Satwant Singh
发明人： Asher Hazanchuk , Ian Ing , Satwant Singh
IPC分类号： G06F7/38
CPC分类号： G06F7/5324 , H03K19/1732 , H03K19/1737
摘要： Various implementations of a digital signal processing (DSP) block architecture of a programmable logic device (PLD) and related methods are provided. In one example, a PLD includes a dedicated DSP block. The DSP block includes a first multiplier adapted to multiply a first plurality of input signals to provide a first plurality of product signals. The DSP block also includes a second multiplier adapted to multiply a second plurality of input signals to provide a second plurality of product signals. The DSP block further includes an arithmetic logic unit (ALU) adapted to operate on the first product signals and the second product signals received at first and second operand inputs, respectively, of the ALU to provide a plurality of output signals.
摘要翻译：提供了可编程逻辑器件（PLD）的数字信号处理（DSP）块结构的各种实施方式和相关方法。在一个示例中，PLD包括专用DSP块。 DSP块包括适于乘以第一多个输入信号以提供第一多个乘积信号的第一乘法器。 DSP块还包括适于乘以第二多个输入信号以提供第二多个乘积信号的第二乘法器。 DSP块还包括算术逻辑单元（ALU），其适于对分别在ALU的第一和第二操作数输入处接收的第一乘积信号和第二乘积信号进行操作，以提供多个输出信号。

12. 发明授权

US07688919B1 Parallel samples, parallel coefficients, time division multiplexing correlator architecture 失效
标题翻译：并行采样，并行系数，时分复用相关器架构
公开(公告)号：US07688919B1
公开(公告)日：2010-03-30
申请号：US09891710
申请日：2001-06-26
申请人： Asher Hazanchuk
发明人： Asher Hazanchuk
IPC分类号： H04L27/06
CPC分类号： H04B1/707 , H04B1/709 , H04B2201/70707
摘要： A method for managing a code sequence is disclosed. First intermediate correlation values for a first plurality of sample sequences are determined during a first clock cycle. Second intermediate correlation values for the first plurality of sample sequences are determined during a second clock cycle. Correlation outputs for the first plurality of sample sequences are determined from the first and second intermediate correlation values.
摘要翻译：公开了一种用于管理代码序列的方法。在第一时钟周期期间确定第一多个采样序列的第一中间相关值。在第二时钟周期期间确定第一多个采样序列的第二中间相关值。从第一和第二中间相关值确定第一多个采样序列的相关输出。

13. 发明授权

US07124161B2 Apparatus and method for implementing efficient arithmetic circuits in programmable logic devices 失效
公开(公告)号：US07124161B2
公开(公告)日：2006-10-17
申请号：US11264778
申请日：2005-10-31
申请人： Chang Choo , Asher Hazanchuk
发明人： Chang Choo , Asher Hazanchuk
IPC分类号： G06F7/38 , G06F7/52
CPC分类号： G06F1/03 , G06F2101/12 , G06F2101/16 , H03K19/1733
摘要： Efficient implementation of arithmetic circuits in programmable logic devices by using Look-Up Tables (LUTs) to store pre-calculated values. A table look-up operation is performed in place of complex arithmetic operations. In this way, at the expense of a few LUTs, many logic elements can be saved. This approach is particularly applicable to circuits for calculating reciprocal values and circuits for performing normalized LMS algorithm.

14. 发明授权

US5537564A Technique for accessing and refreshing memory locations within electronic storage devices which need to be refreshed with minimum power consumption 失效
标题翻译：用于访问和刷新需要以最小功耗刷新的电子存储设备内存储位置的技术
公开(公告)号：US5537564A
公开(公告)日：1996-07-16
申请号：US27666
申请日：1993-03-08
申请人： Asher Hazanchuk , Aleksander M. Movshovich
发明人： Asher Hazanchuk , Aleksander M. Movshovich
IPC分类号： G06F12/06 , G11C11/406 , G06F12/00
CPC分类号： G06F12/0607 , G11C11/406 , Y02B60/1225
摘要： A technique for accessing and refreshing memory locations within a plurality of electronic storage devices which need to be refreshed is disclosed. The technique allows for the accessing of memory locations within the plurality of devices row-by-row such that all memory locations having the same row address within each of the devices are accessed before a memory location with a higher row address is accessed. This accessing technique is implemented through the use of a newly designed address decoder architecture. Once data is stored within the memory locations in this manner, the refreshing technique refreshes only those rows within the plurality of devices which contain data.
摘要翻译：公开了一种用于访问和刷新需要刷新的多个电子存储设备内的存储器位置的技术。该技术允许逐行访问多个设备中的存储器位置，使得在具有较高行地址的存储器位置被访问之前，在每个设备内具有相同行地址的所有存储器位置被访问。该访问技术通过使用新设计的地址解码器架构来实现。一旦以这种方式将数据存储在存储器位置中，则刷新技术仅刷新包含数据的多个设备内的那些行。

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