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    • 13. 发明授权
    • Apparatus, program product and method of estimating the stress intensity factor ratio of a material
    • 估算材料应力强度因子比的装置,程序产品和方法
    • US06718269B2
    • 2004-04-06
    • US10022779
    • 2001-12-13
    • Arvind Kumar Sinha
    • Arvind Kumar Sinha
    • G01L100
    • G01N3/20G01N2203/0023G01N2203/0075G01N2203/0623G01N2203/0682
    • An apparatus, program product, and method for estimating the stress intensity factor ratio (SIFR) of a material. The material is supported on a support and a load is applied to the material using a load member. A pair of strain components are measured using a strain gage attached to the material, and are stored in memory. The strain gage may be a rosette strain gage, for example. A processor calculates a ratio of the stored pair of strain components to thereby provide an estimate of the SIFR of the material. Advantageously, this estimate of the SIFR of the material is readily provided. Also advantageously, the estimate may be provided in a manner that is non-destructive to the material. The processor may additionally calculate the stress level of the material based on the estimated SIFR.
    • 用于估计材料的应力强度因子比(SIFR)的装置,程序产品和方法。 材料支撑在支撑件上,并且使用负载构件将负载施加到材料。 使用附着在材料上的应变计来测量一对应变分量,并存储在存储器中。 应变计例如可以是玫瑰花应变计。 处理器计算存储的一对应变分量的比率,从而提供材料的SIFR的估计。 有利地,容易提供材料的SIFR的这种估计。 还有利地,估计可以以对材料无损的方式提供。 处理器可以基于估计的SIFR另外计算材料的应力水平。
    • 16. 发明授权
    • Three-dimensional stackable die configuration for an electronic circuit board
    • 电子电路板的三维可堆叠模具配置
    • US07438558B1
    • 2008-10-21
    • US11939272
    • 2007-11-13
    • Arvind Kumar Sinha
    • Arvind Kumar Sinha
    • H01R12/00
    • H01R13/22Y10T29/4913
    • A three-dimensional die configuration for mounting electronic components to a circuit board includes a circuit board having at least one circuit board die, a first electronic component mounted at the circuit board die and a first substrate member including a first surface electrically connected to the first chip. The three-dimensional die configuration further includes a double-sided land grid array having a first surface electrically connected to a second surface of the first substrate member. A second substrate member is electrically connected to a second surface of the double-sided land grid array. A second electronic component is electrically connected to a second surface of the second substrate member. A thermal interface member abuts the second chip and is covered by a cap member. The resulting three-dimensional die configuration establishes a multiple electronic component mounting arrangement having a footprint of a single electronic component.
    • 用于将电子部件安装到电路板的三维管芯构造包括具有至少一个电路板裸片,安装在电路板裸片上的第一电子部件和第一基板部件的电路板,第一基板部件包括电连接到第一 芯片。 三维管芯配置还包括双面焊盘栅格阵列,其具有电连接到第一衬底构件的第二表面的第一表面。 第二基板部件电连接到双面焊盘格栅阵列的第二表面。 第二电子部件电连接到第二基板部件的第二表面。 热接口构件邻接第二芯片并被盖构件覆盖。 所得到的三维模具配置建立了具有单个电子部件的占地面积的多个电子部件安装装置。