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11. 发明授权

US07755139B2 Power device with high switching speed and manufacturing method thereof 有权
标题翻译：具有高开关速度的功率器件及其制造方法
公开(公告)号：US07755139B2
公开(公告)日：2010-07-13
申请号：US10557766
申请日：2003-05-19
申请人： Cesare Ronsisvalle
发明人： Cesare Ronsisvalle
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66378 , H01L29/7455
摘要： A power device is formed by a thyristor and by a MOSFET transistor, series-connected between a first and a second current-conduction terminal. The power device moreover has a control terminal connected to an insulated-gate electrode of the MOSFET transistor and receiving a control voltage for turning on/off the device, and a third current-conduction terminal connected to the thyristor for fast extraction of charges during turning-off. Thereby, upon turning off, there are no current tails, and turning off is very fast. The power device does not have parasitic components and consequently has a very high reverse-bias safe-operating area.
摘要翻译：功率器件由晶闸管和串联连接在第一和第二导通端之间的MOSFET晶体管形成。此外，功率器件具有连接到MOSFET晶体管的绝缘栅电极的控制端子，并且接收用于接通/关断器件的控制电压，以及连接到晶闸管的第三导通端子，用于在转动期间快速提取电荷 -off。因此，在关闭时，没有当前尾部，并且关闭非常快。功率器件没有寄生元件，因此具有非常高的反向偏置安全操作区域。

12. 发明申请

US20080246118A1 METHOD FOR REALIZING A CONTACT OF AN INTEGRATED WELL IN A SEMICONDUCTOR SUBSTRATE, IN PARTICULAR FOR A BASE TERMINAL OF A BIPOLAR TRANSISTOR, WITH ENHANCEMENT OF THE TRANSISTOR PERFORMANCES 有权
标题翻译：用于实现半导体衬底中的集成阱的接触的方法，特别是用于双极晶体管的基极端子，具有增强的晶体管性能
公开(公告)号：US20080246118A1
公开(公告)日：2008-10-09
申请号：US12039610
申请日：2008-02-28
申请人： Vincenzo Enea , Cesare Ronsisvalle
发明人： Vincenzo Enea , Cesare Ronsisvalle
IPC分类号： H01L29/73 , H01L21/22
CPC分类号： H01L29/42304 , H01L21/8249 , H01L27/0716 , H01L29/732
摘要： A method realizes a contact of a first well of a first type of dopant integrated in a semiconductor substrate next to a second well of a second type of dopant and forming with it a parasitic diode. The method comprises: formation of the first well; formation of the second well next to the first well; definition of an oxide layer above the first and second wells; and formation of an electric contact layer above the oxide layer in correspondence with the first well for realizing an electric contact with it. The definition step of the oxide layer further comprises a deposition step of this oxide layer above the whole first well and a removal step of at least one portion of the oxide layer in correspondence with a contact area of the first well so that the contact area has a shorter length than a length of the first well.
摘要翻译：一种方法实现了集成在半导体衬底中的第一类掺杂剂的第一阱与第二类掺杂剂的第二阱相邻并与其形成寄生二极管的接触。该方法包括：形成第一井; 在第一井旁边形成第二井; 在第一和第二阱上方的氧化物层的定义; 以及与第一阱对应地形成在氧化物层上方的电接触层，以实现与其的电接触。氧化物层的定义步骤还包括在整个第一阱上方的该氧化物层的沉积步骤和与第一阱的接触面积对应的氧化物层的至少一部分的去除步骤，使得接触区域具有比第一井的长度短的长度。

13. 发明授权

US07095084B2 Emitter switching configuration and corresponding integrated structure 有权
标题翻译：发射极开关配置及相应的集成结构
公开(公告)号：US07095084B2
公开(公告)日：2006-08-22
申请号：US10769563
申请日：2004-01-30
申请人： Cesare Ronsisvalle
发明人： Cesare Ronsisvalle
IPC分类号： H01L31/078
CPC分类号： H03K17/567 , H01L29/7302 , H01L29/739 , H01L29/7803 , H01L29/7808 , H03K17/04166 , H03K17/08142
摘要： An emitter switching configuration having at least one bipolar transistor and a MOS transistor having a common conduction terminal and a Zener diode inserted between a control terminal of the bipolar transistor and the common conduction terminal. A monolithic structure is also provided that is effective in implementing the emitter switching configuration.
摘要翻译：具有至少一个双极晶体管和MOS晶体管的发射极开关配置，其具有公共导通端子和插入在双极晶体管的控制端子和公共导通端子之间的齐纳二极管。还提供了一种有效实现发射极开关配置的单片结构。

14. 发明授权

US08420454B2 Three-terminal power device with high switching speed and manufacturing process 有权
标题翻译：具有高开关速度和制造工艺的三端子功率器件
公开(公告)号：US08420454B2
公开(公告)日：2013-04-16
申请号：US13017982
申请日：2011-01-31
申请人： Cesare Ronsisvalle , Vincenzo Enea
发明人： Cesare Ronsisvalle , Vincenzo Enea
IPC分类号： H01L21/332
CPC分类号： H01L29/7395 , H01L29/742 , H01L29/7455
摘要： An embodiment of a power device having a first current-conduction terminal, a second current-conduction terminal, a control terminal receiving, in use, a control voltage of the power device, and a thyristor device and a first insulated-gate switch device coupled in series between the first and the second conduction terminals; the first insulated-gate switch device has a gate terminal coupled to the control terminal, and the thyristor device has a base terminal. The power device is further provided with: a second insulated-gate switch device, coupled between the first current-conduction terminal and the base terminal of the thyristor device, and having a respective gate terminal coupled to the control terminal; and a Zener diode, coupled between the base terminal of the thyristor device and the second current-conduction terminal so as to enable extraction of current from the base terminal in a given operating condition.
摘要翻译：具有第一导通端子，第二导通端子，控制端子的功率器件的一个实施例，在使用中接收功率器件的控制电压，以及晶闸管器件和第一绝缘栅极开关器件耦合串联在第一和第二导电端子之间; 第一绝缘栅极开关器件具有耦合到控制端子的栅极端子，并且晶闸管器件具有基极端子。功率器件还具有：第二绝缘栅极开关器件，耦合在晶闸管器件的第一通电端子和基极端子之间，并具有耦合到控制端子的相应栅极端子; 以及耦合在晶闸管器件的基极端子和第二导通端子之间的齐纳二极管，以便能够在给定的工作条件下从基极端子提取电流。

15. 发明授权

US07936047B2 Method for realizing a contact of an integrated well in a semiconductor substrate, in particular for a base terminal of a bipolar transistor, with enhancement of the transistor performances 有权
标题翻译：用于实现半导体衬底中的集成阱的接触的方法，特别是用于双极晶体管的基极，与晶体管性能的增强
公开(公告)号：US07936047B2
公开(公告)日：2011-05-03
申请号：US12039610
申请日：2008-02-28
申请人： Vincenzo Enea , Cesare Ronsisvalle
发明人： Vincenzo Enea , Cesare Ronsisvalle
IPC分类号： H01L29/73
CPC分类号： H01L29/42304 , H01L21/8249 , H01L27/0716 , H01L29/732
摘要： A method realizes a contact of a first well of a first type of dopant integrated in a semiconductor substrate next to a second well of a second type of dopant and forming with it a parasitic diode. The method comprises: formation of the first well; formation of the second well next to the first well; definition of an oxide layer above the first and second wells; and formation of an electric contact layer above the oxide layer in correspondence with the first well for realizing an electric contact with it. The definition step of the oxide layer further comprises a deposition step of this oxide layer above the whole first well and a removal step of at least one portion of the oxide layer in correspondence with a contact area of the first well so that the contact area has a shorter length than a length of the first well.
摘要翻译：一种方法实现了集成在半导体衬底中的第一类掺杂剂的第一阱与第二类掺杂剂的第二阱相邻并与其形成寄生二极管的接触。该方法包括：形成第一井; 在第一井旁边形成第二井; 在第一和第二阱上方的氧化物层的定义; 以及与第一阱对应地形成在氧化物层上方的电接触层，以实现与其的电接触。氧化物层的定义步骤还包括在整个第一阱上方的该氧化物层的沉积步骤和与第一阱的接触面积对应的氧化物层的至少一部分的去除步骤，使得接触区域具有比第一井的长度短的长度。

16. 发明申请

US20080169506A1 EMITTER-SWITCHED POWER ACTUATOR 有权
标题翻译：发电机开关电动执行机构
公开(公告)号：US20080169506A1
公开(公告)日：2008-07-17
申请号：US11971158
申请日：2008-01-08
申请人： Cesare Ronsisvalle , Vincenzo Enea
发明人： Cesare Ronsisvalle , Vincenzo Enea
IPC分类号： H01L27/06
CPC分类号： H01L29/7803 , H01L27/0259 , H01L27/0716 , H01L29/7302 , H01L29/739 , H01L29/7808 , H01L29/866
摘要： A power actuator of the emitter-switched type is described, the power actuator comprising at least one high voltage bipolar transistor and a low voltage DMOS transistor connected in cascode configuration between a collector terminal of the bipolar transistor and a source terminal of the DMOS transistor and having respective control terminals. Advantageously, the power actuator further comprises at least a Zener diode, inserted between the source terminal of the DMOS transistor and the control transistor of the bipolar transistor.
摘要翻译：描述了发射极开关型的功率致动器，功率致动器包括至少一个高电压双极晶体管和在双极型晶体管的集电极端子与DMOS晶体管的源极端子之间以级联配置连接的低压DMOS晶体管，以及具有各自的控制端子。有利地，功率致动器还包括插入在DMOS晶体管的源极端子和双极晶体管的控制晶体管之间的至少一个齐纳二极管。

17. 发明授权

US06696741B1 High breakdown voltage PN junction structure, and related manufacturing process 有权
标题翻译：高击穿电压PN结结构及相关制造工艺
公开(公告)号：US06696741B1
公开(公告)日：2004-02-24
申请号：US09443742
申请日：1999-11-19
申请人： Cesare Ronsisvalle , Piero Giorgio Fallica , Davide Patti
发明人： Cesare Ronsisvalle , Piero Giorgio Fallica , Davide Patti
IPC分类号： H01L2358
CPC分类号： H01L29/7802 , H01L21/762 , H01L29/0653
摘要： PN junction structure including a first junction region of a first conductivity type, and a second junction region of a second conductivity type, wherein between said first and second junction regions a grid of buried insulating material regions is provided.
摘要翻译： PN结结构，其包括第一导电类型的第一结区域和第二导电类型的第二结区域，其中在所述第一和第二接合区域之间提供掩埋绝缘材料区域格栅。

18. 发明授权

US5856701A Dielectrically isolated power semiconductor devices 失效
标题翻译：绝缘电力半导体器件
公开(公告)号：US5856701A
公开(公告)日：1999-01-05
申请号：US921726
申请日：1997-08-27
申请人： Cesare Ronsisvalle
发明人： Cesare Ronsisvalle
IPC分类号： H01L21/762 , H01L21/822 , H01L21/84 , H01L27/06 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/76264 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L21/76275 , H01L21/76286 , H01L2924/00011 , H01L2924/0002 , Y10S148/012 , Y10S148/05
摘要： Semiconductor device chips having a first layer of semiconductor material, a second layer of a semiconductor material and an insulating layer disposed therebetween. The first layer of semiconductor material has doped semiconductor regions disposed therein, and the second layer of semiconductor material has a power device disposed therein. The power device is disposed beneath the doped semiconductor region of the first layer. Trenches may be located within the first layer of semiconductor material to electrically isolate different areas having doped semiconductor regions. The insulating layer is typically formed from an oxide.
摘要翻译：半导体器件芯片具有第一半导体材料层，第二层半导体材料和绝缘层。第一层半导体材料具有设置在其中的掺杂半导体区域，并且第二层半导体材料具有设置在其中的功率器件。功率器件设置在第一层的掺杂半导体区域的下方。沟槽可以位于第一半导体材料层内，以电隔离具有掺杂半导体区域的不同区域。绝缘层通常由氧化物形成。

19. 发明授权

US5798287A Method for forming a power MOS device chip 失效
标题翻译：形成功率MOS器件芯片的方法
公开(公告)号：US5798287A
公开(公告)日：1998-08-25
申请号：US861496
申请日：1997-05-22
申请人： Cesare Ronsisvalle
发明人： Cesare Ronsisvalle
IPC分类号： H01L23/051 , H01L29/06 , H01L29/417 , H01L29/78 , H01L21/332
CPC分类号： H01L23/051 , H01L29/41741 , H01L29/7802 , H01L29/0696 , H01L2924/0002 , H01L2924/01074 , H01L2924/13055 , H01L2924/13091
摘要： A power MOS chip and package assembly is provided for packaging a power MOS chip that has high heat dissipation. The assembly maintains a low contact resistance to the chip using compression without damaging the chip. The package assembly includes a thermally conductive body, a chip, an electrically conductive contact washer and an external electrical terminal. The chip includes a semiconductor substrate layer, an insulating layer, a conductive material gate layer and a metal layer. The layers form a plurality of first regions that are functionally inactive and a plurality of second regions. The insulating layer is formed to be thicker in the first regions than in the second regions so that the metal layer is elevated with respect to the substrate layer by a greater amount in the first regions than in the second regions. The contact washer is placed in mechanical contact with the chip so that it exerts pressure against the metal layer in the first regions to create an electrical connection. The terminal is placed in mechanical and electrical contact with the contact washer.
摘要翻译：提供功率MOS芯片和封装组件，用于封装具有高散热功率的功率MOS芯片。组件使用压缩保持对芯片的低接触电阻而不损坏芯片。封装组件包括导热体，芯片，导电接触垫圈和外部电气端子。芯片包括半导体衬底层，绝缘层，导电材料栅极层和金属层。这些层形成功能无效的多个第一区域和多个第二区域。绝缘层形成为在第一区域中比在第二区域中更厚，使得金属层相对于衬底层在第一区域中比在第二区域中更大量地升高。接触垫圈与芯片机械接触，使得其在第一区域中对金属层施加压力以产生电连接。端子与接触垫圈机械和电气接触。

20. 发明授权

US5616512A Power semiconductor devices 失效
标题翻译：功率半导体器件
公开(公告)号：US5616512A
公开(公告)日：1997-04-01
申请号：US360944
申请日：1994-12-21
申请人： Cesare Ronsisvalle
发明人： Cesare Ronsisvalle
IPC分类号： H01L21/762 , H01L21/822 , H01L21/84 , H01L27/06 , H01L27/12 , H01L21/76
CPC分类号： H01L27/1203 , H01L21/76264 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L21/76275 , H01L21/76286 , H01L2924/00011 , H01L2924/0002 , Y10S148/012 , Y10S148/05
摘要： A process for manufacturing integrated circuits includes the following steps. First, an oxide layer is formed on at least one surface of two respective semiconductor material wafers. Next, a single semiconductor material wafer is obtained with a first layer and a second layer of semiconductor material and a buried oxide layer interposed therebetween starting from said two semiconductor material wafers by direct bonding of the oxide layers previously grown. The single wafer is submitted to a controlled reduction of the thickness of the first layer of semiconductor material and the top surface of the first layer of semiconductor material is lapped. Dopant impurities are selectively introduced into selected regions of the first layer of semiconductor material to form the desired integrated components. Trenches are formed laterally delimiting respective portions of the first layer of semiconductor material wherein integrated components are present which are to be electrically isolated from other integrated components. Finally the walls of the trenches are coated with an insulating material and filled with amorphous silicon.
摘要翻译：集成电路的制造工艺包括以下步骤。首先，在两个相应的半导体材料晶片的至少一个表面上形成氧化物层。接下来，通过直接接合先前生长的氧化物层，从所述两个半导体材料晶片开始，通过第一层和第二层半导体材料和介于其间的掩埋氧化物层获得单个半导体材料晶片。使单晶片受到第一半导体材料层的厚度的控制减小，并且第一层半导体材料的顶表面被研磨。掺杂杂质被选择性地引入到第一半导体材料层的选定区域中以形成期望的集成元件。沟槽形成横向限定第一半导体材料层的相应部分，其中存在与其它集成部件电隔离的集成部件。最后，沟槽的壁被绝缘材料涂覆并填充有非晶硅。

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