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11. 发明授权

US07283070B1 Dynamic calibration of I/O power supply level 有权
标题翻译：动态校准I / O电源电平
公开(公告)号：US07283070B1
公开(公告)日：2007-10-16
申请号：US10741680
申请日：2003-12-19
申请人： Aninda K. Roy , Claude R. Gauthier
发明人： Aninda K. Roy , Claude R. Gauthier
IPC分类号： H03M7/40
CPC分类号： G06F1/26 , G06F11/24
摘要： An input/output interface is used to transmit data between a transmitting circuit and a receiving circuit. Selectively during both system startup and system operation, a known bit pattern transmitted by the transmitting circuit is compared to a received bit pattern. The received bit pattern may be seen at the receiving circuit or a voltage regulator that is used to control the power supply level of the input/output interface. Dependent on the comparison of the known bit pattern and the received bit pattern, a bit error rate across the input/output interface is determined, in response to which the voltage regulator adjusts the power supply level of the input/output interface.
摘要翻译：输入/输出接口用于在发送电路和接收电路之间传输数据。在系统启动和系统操作期间选择性地，由发送电路发送的已知位模式与接收的位模式进行比较。可以在接收电路处看到接收到的位模式，或者用于控制输入/输出接口的电源电平的电压调节器。取决于已知位模式与接收位模式的比较，确定输入/输出接口两端的误码率，响应于此，电压调节器调节输入/输出接口的电源电平。

12. 发明授权

US07190719B2 Impedance controlled transmitter with adaptive compensation for chip-to-chip communication 有权
标题翻译：具有自适应补偿的阻抗控制发射机，用于芯片到芯片的通信
公开(公告)号：US07190719B2
公开(公告)日：2007-03-13
申请号：US10338360
申请日：2003-01-08
申请人： Aninda K. Roy , Claude R. Gauthier
发明人： Aninda K. Roy , Claude R. Gauthier
IPC分类号： H03H7/30
CPC分类号： H04L25/03885
摘要： A method and apparatus for adjusting a frequency characteristic of a signal is provided. A transmitter circuit uses a driver circuit and a filter to generate the signal. The frequency characteristic of the signal is adjusted, or “equalized,” using a replica driver that adjusts the driver circuit and a voltage control circuit that adjusts the filter.
摘要翻译：提供了一种用于调整信号的频率特性的方法和装置。发射机电路使用驱动电路和滤波器来产生信号。使用调整驱动电路的复制驱动器和调整滤波器的电压控制电路对信号的频率特性进行调整或“均衡”。

13. 发明授权

US07017086B2 Round-robin updating for high speed I/O parallel interfaces 有权
标题翻译：高速I / O并行接口循环更新
公开(公告)号：US07017086B2
公开(公告)日：2006-03-21
申请号：US10174045
申请日：2002-06-18
申请人： Aninda K. Roy , Claude R. Gauthier , Brian W. Amick
发明人： Aninda K. Roy , Claude R. Gauthier , Brian W. Amick
IPC分类号： G01R31/28
CPC分类号： G01R31/31727
摘要： A technique for adjusting a communication system involves a plurality of links where each link includes a data line adapted to transmit a data signal and a clock line adapted to transmit a clock signal. A test circuit connects to the plurality of links where the test circuit tests at least one of the plurality of links. The test circuit includes an adjustment circuit arranged to generate an adjustable clock signal from the clock signal of the one of the plurality of links based on an offset where the adjustment circuit adjusts a timing of the adjustable clock signal relative to the data signal of the one of the plurality of links. The test circuit is adapted to perform a round-robin testing of the plurality of the links.
摘要翻译：用于调整通信系统的技术涉及多个链路，其中每个链路包括适于传输数据信号的数据线和适于发送时钟信号的时钟线。测试电路连接到测试电路测试多个链路中的至少一个的多个链路。测试电路包括调整电路，该调整电路被布置成基于偏移量从多个链路中的一个链路的时钟信号产生可调节时钟信号，其中调整电路相对于一个数据信号调整可调节时钟信号的定时的多个链接。该测试电路适用于执行多个链路的循环测试。

14. 发明授权

US06842351B2 Method and apparatus for I/O resonance compensation 有权
标题翻译：用于I / O谐振补偿的方法和装置
公开(公告)号：US06842351B2
公开(公告)日：2005-01-11
申请号：US10370901
申请日：2003-02-20
申请人： Claude R. Gauthier , Aninda K. Roy , Brian W. Amick
发明人： Claude R. Gauthier , Aninda K. Roy , Brian W. Amick
IPC分类号： H02J1/02 , H05K1/02 , H00M1/14
CPC分类号： H02J1/02 , H05K1/0216
摘要： A computer system uses a power distribution network arranged to propagate at least one voltage potential to an integrated circuit. A resonance detector is arranged to detect a power supply resonance. A damping circuit is operatively connected to the resonance detector and the power distribution network. The damping circuit resides external to the integrated circuit and dampens the power supply resonance under control of the resonance detector.
摘要翻译：计算机系统使用布置成将至少一个电压电势传播到集成电路的配电网络。谐振检测器被布置成检测电源谐振。阻尼电路可操作地连接到谐振检测器和配电网络。阻尼电路位于集成电路的外部，并在谐振检测器的控制下抑制电源谐振。

15. 发明授权

US06842057B1 Analog state recovery technique for DLL design 有权
标题翻译：用于DLL设计的模拟状态恢复技术
公开(公告)号：US06842057B1
公开(公告)日：2005-01-11
申请号：US10638805
申请日：2003-08-11
申请人： Claude R. Gauthier , Aninda K. Roy
发明人： Claude R. Gauthier , Aninda K. Roy
IPC分类号： H03L7/081 , H03L7/089 , H03L7/093 , H03L7/14 , H03L7/06
CPC分类号： H03L7/14 , H03L7/0812 , H03L7/0891 , H03L7/093
摘要： A method and apparatus stores a voltage potential generated by a delay locked loop in order to reduce the time required for the delay locked loop to recover from a lost clock state. A clock path is arranged to carry a clock signal. The delay locked loop operatively connects to the clock path where the delay locked loop is arranged to generate a voltage potential dependent on a phase difference between the clock signal and a delayed clock signal output of the delay locked loop. An analog state storage apparatus operatively connects to the delay locked loop and is arranged to store the voltage potential. Also, the analog state storage apparatus is arranged to output the stored voltage potential to the delay locked loop in response to a loss of at least one of the clock signal and the delayed clock signal.
摘要翻译：一种方法和装置存储由延迟锁定环产生的电压电位，以便减少延迟锁定环从丢失时钟状态恢复所需的时间。时钟路径被布置成携带时钟信号。延迟锁定环路可操作地连接到时钟路径，其中延迟锁定环路被布置成产生取决于时钟信号和延迟锁定环路的延迟时钟信号输出之间的相位差的电压电位。模拟状态存储装置可操作地连接到延迟锁定环路并且被布置成存储电压电位。此外，模拟状态存储装置被布置为响应于时钟信号和延迟的时钟信号中的至少一个的丢失而将存储的电压电压输出到延迟锁定环路。

16. 发明授权

US07590392B2 Transmitter compensation 有权
标题翻译：变送器补偿
公开(公告)号：US07590392B2
公开(公告)日：2009-09-15
申请号：US11263791
申请日：2005-10-31
申请人： Navindra Navaratnam , Aninda K. Roy
发明人： Navindra Navaratnam , Aninda K. Roy
IPC分类号： H04B1/04 , H04B17/00 , H03K17/16 , G06G7/12
CPC分类号： H04B3/46
摘要： In some embodiments, a chip with a transmitter having a transmitter driver is provided. Also provided is a general compensation circuit coupled to the transmitter to generally compensate the transmitter driver and a specific compensation circuit coupled to the transmitter driver to specifically compensate the transmitter driver. Other embodiments are disclosed and claimed herein.
摘要翻译：在一些实施例中，提供具有发射机的具有发射机驱动器的芯片。还提供了耦合到发射器的通用补偿电路，以大体上补偿发射器驱动器和耦合到发射器驱动器的特定补偿电路，以特别地补偿发射器驱动器。本文公开和要求保护的其它实施例。

17. 发明授权

US06756824B2 Self-biased driver amplifiers for high-speed signaling interfaces 有权
标题翻译：用于高速信号接口的自偏置驱动器放大器
公开(公告)号：US06756824B2
公开(公告)日：2004-06-29
申请号：US10292261
申请日：2002-11-12
申请人： Aninda K. Roy , Samudyatha Suryanarayana
发明人： Aninda K. Roy , Samudyatha Suryanarayana
IPC分类号： H03B100
CPC分类号： H03K19/00384 , H03K19/00323
摘要： Disclosed are novel methods and apparatus for efficiently providing self-biased driver amplifiers for high-speed signaling interfaces. In an embodiment of the present invention, a self-biased amplifier driver is disclosed. The driver includes a sensing circuit to sense a presence of noise in a power supply signal. The sensing circuit may include a current source to adjust an output signal of the sensing circuit in accordance with the power supply noise. The driver may further include: an amplifier coupled to the sensing circuit to amplify the sensing circuit output signal, a pre-driver to receive a data signal, and a driver coupled to the amplifier and the pre-driver to receive an amplifier output signal and a pre-driver output signal.
摘要翻译：公开了用于高速提供用于高速信令接口的自偏置驱动器放大器的新颖方法和装置。在本发明的实施例中，公开了一种自偏置放大器驱动器。驱动器包括用于感测电源信号中的噪声的感测电路。感测电路可以包括电流源，以根据电源噪声来调节感测电路的输出信号。驱动器还可以包括：耦合到感测电路以放大感测电路输出信号的放大器，用于接收数据信号的预驱动器和耦合到放大器和预驱动器的驱动器以接收放大器输出信号的放大器，预驱动器输出信号。

18. 发明授权

US06762623B2 High-resolution single-ended source-synchronous receiver 有权
标题翻译：高分辨率单端源同步接收机
公开(公告)号：US06762623B2
公开(公告)日：2004-07-13
申请号：US10320148
申请日：2002-12-16
申请人： Samudyatha Suryanarayana , Aninda K. Roy
发明人： Samudyatha Suryanarayana , Aninda K. Roy
IPC分类号： H03K19082
CPC分类号： H04L25/0292
摘要： Disclosed are novel methods and apparatus for efficiently providing high-resolution single-ended source synchronous receivers. In an embodiment of the present invention, a source-synchronous receiver is disclosed. The receiver includes: a first amplifier to receive a clock signal and a data signal, the first amplifier providing a first output signal; a second amplifier to receive a complementary clock signal and the data signal, the second amplifier providing a second output signal; a third amplifier to receive the clock signal and the data signal, the third amplifier providing a third output signal, the second and third output signals being combined to provide a fifth output; and a fourth amplifier to receive the complementary clock signal and the data signal, the fourth amplifier providing a fourth output signal, the first and fourth output signals being combined to provide a sixth output signal.
摘要翻译：公开了用于有效提供高分辨率单端源同步接收机的新颖方法和装置。在本发明的实施例中，公开了一种源同步接收机。所述接收机包括：第一放大器，用于接收时钟信号和数据信号，所述第一放大器提供第一输出信号; 第二放大器，用于接收互补时钟信号和所述数据信号，所述第二放大器提供第二输出信号; 第三放大器，用于接收所述时钟信号和所述数据信号，所述第三放大器提供第三输出信号，所述第二和第三输出信号被组合以提供第五输出; 以及第四放大器，用于接收所述互补时钟信号和所述数据信号，所述第四放大器提供第四输出信号，所述第一和第四输出信号被组合以提供第六输出信号。

19. 发明授权

US06788123B2 Unity gain interpolator for delay locked loops 有权
公开(公告)号：US06788123B2
公开(公告)日：2004-09-07
申请号：US10338224
申请日：2003-01-08
申请人： Aninda K. Roy
发明人： Aninda K. Roy
IPC分类号： H03K312
CPC分类号： H03L7/0812 , H03H11/265
摘要： A method and apparatus for delaying a clock signal involves a first clock path arranged to propagate a first clock signal; a second clock path arranged to propagate a second clock signal; and an interpolator arranged as a unity gain operational amplifier. An amount of delay between the first and second clock signals is determined by a control voltage potential.

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