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11. 发明申请

US20070290272A1 INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT 有权
标题翻译：集成薄膜电阻与直接接触
公开(公告)号：US20070290272A1
公开(公告)日：2007-12-20
申请号：US11846595
申请日：2007-08-29
申请人： Eric Coker , Douglas Coolbaugh , Ebenezer Eshun , Zhong-Xiang He , Matthew Moon , Anthony Stamper
发明人： Eric Coker , Douglas Coolbaugh , Ebenezer Eshun , Zhong-Xiang He , Matthew Moon , Anthony Stamper
IPC分类号： H01L29/00
CPC分类号： H01L27/016
摘要： A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.
摘要翻译：适用于灵活集成的BEOL薄膜电阻依赖于第一层ILD。 ILD的第一层的厚度和电阻器厚度相结合，以匹配所涉及的层中的通孔的标称设计厚度。第二层ILD匹配电阻器厚度，并平坦化到电阻器的顶表面。 ILD的第三层具有等于该层上互连的标称值的厚度。同时形成用于与电阻器接触的双镶嵌互连孔和孔，电阻器中的蚀刻停止上盖层保护电阻层，同时形成双镶嵌孔中的通孔。

12. 发明申请

US20070190760A1 INTEGRATED PARALLEL PLATE CAPACITORS 有权
标题翻译：集成并联板电容器
公开(公告)号：US20070190760A1
公开(公告)日：2007-08-16
申请号：US11275544
申请日：2006-01-13
申请人： Douglas Coolbaugh , Hanyi Ding , Ebenezer Eshun , Michael Gordon , Zhong-Xiang He , Anthony Stamper
发明人： Douglas Coolbaugh , Hanyi Ding , Ebenezer Eshun , Michael Gordon , Zhong-Xiang He , Anthony Stamper
IPC分类号： H01L21/425
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A parallel plate capacitor formed in the back end of an integrated circuit employs conductive capacitor plates that are formed simultaneously with the other interconnects on that level of the back end (having the same material, thickness, etc). The capacitor plates are set into the interlevel dielectric using the same process as the other interconnects on that level of the back end (preferably dual damascene). Some versions of the capacitors have perforations in the plates and vertical conductive members connecting all plates of the same polarity, thereby increasing reliability, saving space and increasing the capacitive density compared with solid plates.
摘要翻译：形成在集成电路的后端的平行电容器采用与后端（具有相同材料，厚度等）的该级别上的其它互连件同时形成的导电电容器板。使用与后端（优选双镶嵌）级别上的其它互连件相同的工艺将电容器板设置在层间电介质中。一些版本的电容器在板中具有穿孔，并且垂直导电构件连接相同极性的所有板，从而与实心板相比增加了可靠性，节省了空间并增加了电容密度。

13. 发明申请

US20070262416A1 METHOD AND STRUCTURE FOR CREATION OF A METAL INSULATOR METAL CAPACITOR 有权
标题翻译：金属绝缘子金属电容器的制造方法与结构
公开(公告)号：US20070262416A1
公开(公告)日：2007-11-15
申请号：US11382544
申请日：2006-05-10
申请人： Ebenezer Eshun , Ronald Bolam , Douglas Coolbaugh , Keith Downes , Natalie Feilchenfeld , Zhong-Xiang He
发明人： Ebenezer Eshun , Ronald Bolam , Douglas Coolbaugh , Keith Downes , Natalie Feilchenfeld , Zhong-Xiang He
IPC分类号： H01L29/00
CPC分类号： H01L28/60
摘要： The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.
摘要翻译：本发明涉及一种改进的电容器，其减少边缘缺陷并防止产量失效。本发明的第一实施例包括与导电层与绝缘体的界面相邻的保护层，而本发明的第二实施例包括位于导电层上的绝缘体上的保护层。

14. 发明申请

US20070158714A1 ONE-MASK HIGH-K METAL-INSULATOR-METAL CAPACITOR INTEGRATION IN COPPER BACK-END-OF-LINE PROCESSING 审中-公开
标题翻译：铜掩模高级金属绝缘子 - 金属电容器集成在铜后处理中
公开(公告)号：US20070158714A1
公开(公告)日：2007-07-12
申请号：US11164382
申请日：2005-11-21
申请人： Ebenezer Eshun , Jessie Abbotts , Daniel Colello , Douglas Coolbaugh , Zhong-Xiang He , Matthew Moon , Charles Musante , Robert Rassel
发明人： Ebenezer Eshun , Jessie Abbotts , Daniel Colello , Douglas Coolbaugh , Zhong-Xiang He , Matthew Moon , Charles Musante , Robert Rassel
IPC分类号： H01L29/94
CPC分类号： H01L28/60 , H01L21/76895
摘要： A MIM capacitor technique is described wherein bottom plates (electrodes) are composed of gate conductor material, and are formed in the same layer, in the same way, using the same masking and processing steps as transistor gates. The top plates (electrodes) are formed using a simple single-mask, single-damascene process. Electrical connections to both electrodes of the MIM capacitor are made via conventional BEOL metallization, requiring no additional dedicated process steps. The bottom plates (formed of gate conductor material) of the MIM capacitors overlie STI regions formed at the same time as STI regions between transistors. Method and apparatus are described.
摘要翻译：描述了MIM电容器技术，其中底板（电极）由栅极导体材料构成，并且以相同的方式使用与晶体管栅极相同的掩模和处理步骤形成在相同的层中。顶板（电极）使用简单的单掩模，单镶嵌工艺形成。与MIM电容器的两个电极的电连接通过常规BEOL金属化制成，不需要额外的专用工艺步骤。 MIM电容器的底板（由栅极导体材料形成）覆盖与晶体管之间的STI区域同时形成的STI区域。描述了方法和装置。

15. 发明申请

US20050230785A1 RESISTOR TUNING 有权
标题翻译：电阻调谐
公开(公告)号：US20050230785A1
公开(公告)日：2005-10-20
申请号：US10709115
申请日：2004-04-14
申请人： Douglas Coolbaugh , Ebenezer Eshun , Robert Rassel , Anthony Stamper
发明人： Douglas Coolbaugh , Ebenezer Eshun , Robert Rassel , Anthony Stamper
IPC分类号： H01C17/26 , H01L29/76
CPC分类号： H01C17/267
摘要： A structure for resistors and the method for tuning the same. The resistor comprises an electrically conducting region coupled to a liner region. Both the electrically conducting region and the liner region are electrically coupled to first and second contact regions. A voltage difference is applied between the first and second contact regions. As a result, a current flows between the first and second contact regions in the electrically conducting region. The voltage difference and the materials of the electrically conducting region and the liner region are such that electromigration occurs only in the electrically conducting region. As a result, a void region within the electrically conducting region expands in the direction of the flow of the charged particles constituting the current. Because the resistor loses a conducting portion of the electrically conducting region to the void region, the resistance of the resistor is increased (i.e., tuned).
摘要翻译：电阻器结构及其调谐方法。电阻器包括耦合到衬垫区域的导电区域。导电区域和衬里区域都电耦合到第一和第二接触区域。在第一和第二接触区域之间施加电压差。结果，电流在导电区域中的第一和第二接触区域之间流动。导电区域和衬垫区域的电压差和材料使得电迁移仅在导电区域中发生。结果，导电区域内的空隙区域在构成电流的带电粒子的流动方向上膨胀。因为电阻器将导电区域的导电部分损失到空隙区域，电阻器的电阻增加（即调谐）。

16. 发明申请

US20080042798A1 HEAT SINK FOR INTEGRATED CIRCUIT DEVICES 失效
公开(公告)号：US20080042798A1
公开(公告)日：2008-02-21
申请号：US11848263
申请日：2007-08-31
申请人： Douglas Coolbaugh , Ebenezer Eshun , Terence Hook , Robert Rassel , Edmund Sprogis , Anthony Stamper , William Murphy
发明人： Douglas Coolbaugh , Ebenezer Eshun , Terence Hook , Robert Rassel , Edmund Sprogis , Anthony Stamper , William Murphy
IPC分类号： H01C1/08
CPC分类号： H01C7/1013 , H01C1/084 , H01L2924/0002 , Y10T29/49083 , Y10T29/49085 , Y10T29/49099 , Y10T29/49144 , Y10T29/49147 , H01L2924/00
摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.

17. 发明申请

US20070187800A1 RESISTOR TUNING 审中-公开
标题翻译：电阻调谐
公开(公告)号：US20070187800A1
公开(公告)日：2007-08-16
申请号：US11737304
申请日：2007-04-19
申请人： Douglas Coolbaugh , Ebenezer Eshun , Robert Rassel , Anthony Stamper
发明人： Douglas Coolbaugh , Ebenezer Eshun , Robert Rassel , Anthony Stamper
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01C17/267
摘要： A structure for resistors and the method for tuning the same. The resistor comprises an electrically conducting region coupled to a liner region. Both the electrically conducting region and the liner region are electrically coupled to first and second contact regions. A voltage difference is applied between the first and second contact regions. As a result, a current flows between the first and second contact regions in the electrically conducting region. The voltage difference and the materials of the electrically conducting region and the liner region are such that electromigration occurs only in the electrically conducting region. As a result, a void region within the electrically conducting region expands in the direction of the flow of the charged particles constituting the current. Because the resistor loses a conducting portion of the electrically conducting region to the void region, the resistance of the resistor is increased (i.e., tuned).
摘要翻译：电阻器结构及其调谐方法。电阻器包括耦合到衬垫区域的导电区域。导电区域和衬里区域都电耦合到第一和第二接触区域。在第一和第二接触区域之间施加电压差。结果，电流在导电区域中的第一和第二接触区域之间流动。导电区域和衬垫区域的电压差和材料使得电迁移仅在导电区域中发生。结果，导电区域内的空隙区域在构成电流的带电粒子的流动方向上膨胀。因为电阻器将导电区域的导电部分损失到空隙区域，电阻器的电阻增加（即调谐）。

18. 发明申请

US20060152333A1 HEAT SINK FOR INTEGRATED CIRCUIT DEVICES 有权
标题翻译：集成电路设备的散热
公开(公告)号：US20060152333A1
公开(公告)日：2006-07-13
申请号：US10905546
申请日：2005-01-10
申请人： Douglas Coolbaugh , Ebenezer Eshun , Terence Hook , Robert Rassel , Edmund Sprogis , Anthony Stamper , William Murphy
发明人： Douglas Coolbaugh , Ebenezer Eshun , Terence Hook , Robert Rassel , Edmund Sprogis , Anthony Stamper , William Murphy
IPC分类号： H01C1/08
CPC分类号： H01C7/1013 , H01C1/084 , H01L2924/0002 , Y10T29/49083 , Y10T29/49085 , Y10T29/49099 , Y10T29/49144 , Y10T29/49147 , H01L2924/00
摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.
摘要翻译：提供带散热片的电阻。散热器包括具有导热性高的金属或其它热导体的导电路径。为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

19. 发明申请

US20050067701A1 METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATION 有权
标题翻译：金属绝缘体 - 金属电容器和制造方法
公开(公告)号：US20050067701A1
公开(公告)日：2005-03-31
申请号：US10605444
申请日：2003-09-30
申请人： Douglas Coolbaugh , Ebenezer Eshun , Jeffrey Gambino , Zhong-Xiang He , Vidhya Ramachandran
发明人： Douglas Coolbaugh , Ebenezer Eshun , Jeffrey Gambino , Zhong-Xiang He , Vidhya Ramachandran
IPC分类号： H01L21/02 , H01L21/768 , H01L23/52 , H01L21/44
CPC分类号： H01L21/7687 , H01L23/5223 , H01L23/53238 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.
摘要翻译：一种MIM电容器的方法和结构，该结构包括：电子器件，包括：形成在半导体衬底上的层间电介质层; 形成在所述层间电介质层中的铜底电极，所述底电极共平面的上表面与所述层间电介质层的顶面形成; 与底部电极的顶表面直接接触的导电扩散阻挡层; 与所述导电扩散阻挡层的顶表面直接接触的MIM电介质; 以及与MIM电介质的顶表面直接接触的顶部电极。导电扩散阻挡层可以凹进到铜底电极或设置的另外的凹入的导电扩散阻挡层中。还公开了兼容的电阻器和对准标记结构。

20. 发明申请

US20060270247A1 HI-K DIELECTRIC LAYER DEPOSITION METHODS 失效
标题翻译： HI-K介电层沉积方法
公开(公告)号：US20060270247A1
公开(公告)日：2006-11-30
申请号：US10908789
申请日：2005-05-26
申请人： Douglas Coolbaugh , Ebenezer Eshun , Kenneth Stein , Kunal Vaed
发明人： Douglas Coolbaugh , Ebenezer Eshun , Kenneth Stein , Kunal Vaed
IPC分类号： H01L21/336
CPC分类号： H01L21/02181 , C23C16/405 , C23C16/45523 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02183 , H01L21/02189 , H01L21/28194 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L29/513 , H01L29/517
摘要： Methods of forming a high dielectric constant dielectric layer are disclosed including providing a process chamber including a holder for supporting a substrate, introducing a first gas comprising a high dielectric constant (Hi-K) dielectric precursor and an oxygen (O2) oxidant into the process chamber to form a first portion of the high dielectric constant dielectric layer on the substrate, and switching from a flow of the first gas to a flow of a second gas comprising the Hi-K dielectric precursor and an ozone (O3) oxidant to form a second portion of the high dielectric constant dielectric layer on the first portion. In an alternative embodiment, another portion can be formed on the second portion using the oxygen oxidant. The invention increases throughput by at least 20% without reliability or leakage degradation and without the need for additional equipment.
摘要翻译：公开了形成高介电常数电介质层的方法，包括提供包括用于支撑衬底的保持器的处理室，引入包含高介电常数（Hi-K）电介质前体和氧（O 2） / SUB>）氧化剂进入处理室以形成衬底上的高介电常数电介质层的第一部分，并且从第一气体的流动切换到包括Hi-K电介质前体的第二气体的流动，以及臭氧（O 3 3）氧化剂以形成第一部分上的高介电常数介电层的第二部分。在替代实施例中，可以使用氧氧化剂在第二部分上形成另一部分。本发明将产量提高了至少20％，而没有可靠性或泄漏降级，并且不需要额外的设备。

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