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11. 发明授权

US6067409A Advanced modular cell placement system 失效
标题翻译：先进的模块化放置系统
公开(公告)号：US6067409A
公开(公告)日：2000-05-23
申请号：US798598
申请日：1997-02-11
申请人： Ranko Scepanovic , Ivan Pavisic , James S. Koford , Alexander E. Andreev , Edwin Jones
发明人： Ranko Scepanovic , Ivan Pavisic , James S. Koford , Alexander E. Andreev , Edwin Jones
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system for determining an affinity associated with relocating a cell located on a surface of a semiconductor chip to a different location on the surface is disclosed herein. Each cell may be part of a cell net containing multiple cells. The system initially defines a bounding box containing all cells in the net which contains the cell. The system then establishes a penalty vector based on the bounding box and borders of a region containing the cell, computes a normalized sum of penalties for all nets having the cell as a member, and calculates the affinity based on the normalized sum of penalties. Also included in the disclosed system are methods and apparatus for capacity and utilization planning of the use of the floor, or the surface area, and the methods and apparatus for parallelizing the process of affinity based placements using multiple processors. Finally, method and apparatus for connecting the cells based on a Steiner Tree method is disclosed.
摘要翻译：本文公开了一种用于确定与将位于半导体芯片的表面上的单元重新定位到表面上的不同位置的亲和度的系统。每个细胞可以是包含多个细胞的细胞网的一部分。系统最初定义了包含网络中包含单元格的所有单元格的边界框。然后，该系统基于边界框和包含单元格的区域的边界来建立惩罚向量，计算具有该单元作为成员的所有网络的归一化惩罚总和，并且基于标准化的惩罚总和来计算亲和度。所公开的系统中还包括用于使用楼层或表面积的容量和利用规划的方法和装置，以及用于使用多个处理器并行化基于亲和力的布置的过程的方法和装置。最后，公开了基于Steiner Tree方法连接单元的方法和装置。

12. 发明授权

US5796625A Physical design automation system and process for designing integrated circuit chip using simulated annealing with "chessboard and jiggle" optimization 失效
标题翻译：物理设计自动化系统和使用模拟退火设计集成电路芯片的过程用“棋盘和摆动”优化
公开(公告)号：US5796625A
公开(公告)日：1998-08-18
申请号：US609359
申请日：1996-03-01
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev , Ivan Pavisic
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev , Ivan Pavisic
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A cell placement for an integrated circuit chip is divided into two "chessboard" patterns or "jiggles". Each pattern resembles a chessboard in that it consists of alternating regions of different types or "colors" such that no region of a given color has an edge common with another region of the same color. The jiggles are offset relative to each other such that the regions of one jiggle partially overlap at least two regions of the other jiggle. Simulated annealing is performed sequentially for each color of each jiggle. During each operation, a plurality of parallel processors operate on the regions simultaneously using a previous copy of the entire chip, with one processor being assigned to one or more regions. At the end of each operation, the copy of the chip is updated. The chessboard patterns eliminate unproductive cell moves resulting from adjacent regions having a common edge. The jiggles enable cells to move to their optimal positions from their initial region to any other region on the chip. The regions can have rectangular, triangular or hexagonal shapes. An initial temperature for the actual simulated annealing operation is determined by performing simulated annealing without cell swaps with different temperature, and selecting the temperature at which a cost function such as total wirelength does not significantly change.
摘要翻译：集成电路芯片的单元布局分为两个“棋盘”图案或“跳棋”。每个图案类似于棋盘，其由不同类型或“颜色”的交替区域组成，使得给定颜色的区域不具有与相同颜色的另一区域相同的边缘。跳块相对于彼此偏移，使得一个颤动的区域部分地与另一个摇摆的至少两个区域重叠。对每个抖动的每个颜色依次执行模拟退火。在每个操作期间，多个并行处理器使用整个芯片的先前副本同时在该区域上操作，一个处理器被分配给一个或多个区域。在每个操作结束时，更新芯片的副本。棋盘图案消除由具有共同边缘的相邻区域产生的非生产性细胞移动。这些跳跃使得电池从它们的初始区域移动到其最佳位置到芯片上的任何其它区域。这些区域可以具有矩形，三角形或六边形形状。实际模拟退火操作的初始温度是通过进行模拟退火而不使用不同温度的电池互换来确定的，并且选择诸如总线长度的成本函数不会显着改变的温度。

13. 发明授权

US07028274B1 RRAM backend flow 失效
标题翻译： RRAM后端流
公开(公告)号：US07028274B1
公开(公告)日：2006-04-11
申请号：US11054460
申请日：2005-02-09
申请人： Alexander Andreev , Ranko Scepanovic , Ivan Pavisic , Vojislav Vukovic
发明人： Alexander Andreev , Ranko Scepanovic , Ivan Pavisic , Vojislav Vukovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method for transforming a customer's memory design into an RRAM memory design. A port mapping table is created that lists the ports of the customer memories, and an instance types table is created that lists the customer memories. For each customer memory that is listed in the instance types table, any virtual buffer nets are removed, and any virtual buffers are removed. Any loose nets so created are reconnected to an RRAM cell in the RRAM memory design. The customer memory instance are then removed. A constraints file is updated from customer memory port designations to RRAM port designations. Automated test logic is inserted into the RRAM memory design, layout on the RRAM memory design is performed, and timing constraints on the RRAM memory design are satisfied. A modified version of the RRAM memory design is returned to the customer for verification. The modified version is made using the port mapping table. Each RRAM matrix is replaced with the customer memories it replaced, the removed virtual buffer nets and virtual buffers are left out, and other parts of the RRAM memory design are left unchanged.
摘要翻译：将客户的存储器设计转换为RRAM存储器设计的方法。创建一个端口映射表，其中列出了客户端口的存储器，并创建了一个列出客户内存的实例类型表。对于实例类型表中列出的每个客户内存，将删除任何虚拟缓冲区网络，并删除任何虚拟缓冲区。任何如此创建的松散网络都将重新连接到RRAM内存设计中的RRAM单元。然后删除客户内存实例。约束文件从客户内存端口名称更新为RRAM端口名称。将自动测试逻辑插入到RRAM存储器设计中，执行RRAM存储器设计的布局，并满足RRAM存储器设计的时序约束。将修改版本的RRAM存储器设计返回给客户进行验证。修改版本使用端口映射表进行。每个RRAM矩阵被替换的客户存储器替代，删除的虚拟缓冲器网络和虚拟缓冲器被省略，并且RRAM存储器设计的其他部分保持不变。

14. 发明授权

US06292929B1 Advanced modular cell placement system 有权
公开(公告)号：US06292929B1
公开(公告)日：2001-09-18
申请号：US09444975
申请日：1999-11-22
申请人： Ranko Scepanovic , Ivan Pavisic , James S. Koford , Alexander E. Andreev , Edwin Jones
发明人： Ranko Scepanovic , Ivan Pavisic , James S. Koford , Alexander E. Andreev , Edwin Jones
IPC分类号： G06F1750
摘要： A system for determining an affinity associated with relocating a cell located on a surface of a semiconductor chip to a different location on the surface is disclosed herein. Each cell may be part of a cell net containing multiple cells. The system initially defines a bounding box containing all cells in the net which contains the cell. The system then establishes a penalty vector based on the bounding box and borders of a region containing the cell, computes a normalized sum of penalties for all nets having the cell as a member, and calculates the affinity based on the normalized sum of penalties. Also included in the disclosed system are methods and apparatus for capacity and utilization planning of the use of the floor, or the surface area, and the methods and apparatus for parallelizing the process of affinity based placements using multiple processors. Finally, method and apparatus for connecting the cells based on a Steiner Tree method is disclosed.

15. 发明授权

US5898597A Integrated circuit floor plan optimization system 失效
标题翻译：集成电路平面图优化系统
公开(公告)号：US5898597A
公开(公告)日：1999-04-27
申请号：US798652
申请日：1997-02-11
申请人： Ranko Scepanovic , Alexander E. Andreev , Ivan Pavisic
发明人： Ranko Scepanovic , Alexander E. Andreev , Ivan Pavisic
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method for planning floor allocation of an integrated circuit to each function is disclosed. To provide enough core space to each of the functions and to meet some cost functions such as space utilization requirement of each of the functions, the disclosed method divides the core space to a grid of elementary regions. Then, pieces of the core space are defined and the pieces containing the borders and the overlapping areas of the functions are identified. Then, the identified pieces are used shift the allocated capacities of the functions as to shift excess capacity or core space from the functions with excess capacity to the functions with a shortage of capacity.
摘要翻译：公开了一种用于规划每个功能的集成电路的楼层分配的方法。为了为每个功能提供足够的核心空间并且满足诸如每个功能的空间利用要求的一些成本函数，所公开的方法将核心空间划分为基本区域的网格。然后，确定核心空间的块，并且识别包含边界的部分和功能的重叠区域。然后，使用所识别的部件将功能的分配能力转移到将过剩容量或核心空间从具有过剩容量的功能转移到容量不足的功能中。

16. 发明授权

US06760896B2 Process layout of buffer modules in integrated circuits 失效
公开(公告)号：US06760896B2
公开(公告)日：2004-07-06
申请号：US10254607
申请日：2002-09-25
申请人： Alexander E. Andreev , Ivan Pavisic , Ranko Scepanovic
发明人： Alexander E. Andreev , Ivan Pavisic , Ranko Scepanovic
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： A bus is defined on a core of an integrated circuit. Routing lines are defined through the core, and net wires are routed through the core along respective routing lines. Buffer columns are defined in the core across a plurality of nets, and buffers are placed in the buffer columns so that an input and output to a respective buffer are on different routing lines. The buffers have at least one free routing line and the net wires are redistribution across the buffer so that (i) the net wire to be buffered is re-routed to the input and output of the buffer, (ii) the net wires on routing lines containing the input and output of the buffer are re-routed to the routing line of the net wire to be buffered and the free routing line, and (iii) all other net wires are routed along their respective routing lines.

17. 发明授权

US06186676B1 Method and apparatus for determining wire routing 失效
标题翻译：用于确定线路布线的方法和装置
公开(公告)号：US06186676B1
公开(公告)日：2001-02-13
申请号：US08906947
申请日：1997-08-06
申请人： Alexander E. Andreev , Ivan Pavisic , Ranko Scepanovic
发明人： Alexander E. Andreev , Ivan Pavisic , Ranko Scepanovic
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that wire routine be done correctly to avoid any congestion of wires. Congestion of wires can be determined by actually routing of the wires to connect the cells; however, the routing process is computationally expensive. For determination of congestion, the only required information are the location of the connections, or edges, to connect the pins of the IC. The present invention discloses a method to quickly provide a good estimate of the location of the edges, or connections for an IC. The present invention provides for a method to determine all the edges and superedges (bounding boxes, or areas where an edge will take space) of an IC without requiring to determine the actual routing of the wires of an IC.
摘要翻译：集成电路芯片（IC）需要适当放置许多单元（电路组件组）和复杂的导线布线以连接单元的引脚。由于需要大量的单元和复杂的连接，因此必须正确地进行线路程序，以避免导线的拥塞。可以通过实际布线连接电池来确定电线的拥塞; 然而，路由过程在计算上是昂贵的。为了确定拥塞，唯一需要的信息是连接IC的引脚的连接或边缘的位置。本发明公开了一种快速提供对于IC的边缘或连接的位置的良好估计的方法。本发明提供了一种确定集成电路的所有边缘和覆盖（边界将占据空间的区域）的方法，而不需要确定IC的导线的实际布线。

18. 发明授权

US6123736A Method and apparatus for horizontal congestion removal 失效
标题翻译：水平堵塞消除的方法和装置
公开(公告)号：US6123736A
公开(公告)日：2000-09-26
申请号：US906949
申请日：1997-08-06
申请人： Ivan Pavisic , Ranko Scepanovic , Alexander E. Andreev
发明人： Ivan Pavisic , Ranko Scepanovic , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that placement of the cell and the wire routine be done correctly to avoid any congestion of wires. Placement of the cells and the routing of the wires to avoid congestion can be accomplished by determining congestion of various regions, or pieces, of the IC's after an initial placement of the cells and routing of the wires. The present invention discloses a method and apparatus to define the regions, or pieces, of the IC, determine various density measurement of the pieces, and adjust the sizes of the pieces to reduce congestion of congested pieces by reallocating space from uncongested pieces to congested pieces. In addition, the present invention discloses the technique of adjusting the sizes of the piece to minimize disturbing the placement and wire routing while the congestion is being reduced. This is accomplished by comparing the vertical location of each of the pieces to the vertical location of the pieces next to it.
摘要翻译：集成电路芯片（IC）需要适当放置许多单元（电路组件组）和复杂的导线布线以连接单元的引脚。由于需要大量的单元和复杂的连接，所以必须正确地进行单元和电线程序的布置，以避免导线堵塞。可以通过在单元的初始放置和导线的布线之后确定IC的各个区域或多个块的拥塞来实现单元的放置和布线以避免拥塞。本发明公开了一种用于限定IC的区域或片段的方法和装置，确定片段的各种密度测量，并调整片段的尺寸，以通过将空隙重新分配成未充塞的片段到拥塞的部分来减少拥塞片的拥塞。此外，本发明公开了一种在减少拥塞的情况下调整片的大小以最小化扰乱布局和布线的技术。这是通过将每个片段的垂直位置与其旁边的片段的垂直位置进行比较来实现的。

19. 发明授权

US5875118A Integrated circuit cell placement parallelization with minimal number of conflicts 失效
标题翻译：集成电路单元放置与最少数量的冲突并行化
公开(公告)号：US5875118A
公开(公告)日：1999-02-23
申请号：US798653
申请日：1997-02-11
申请人： Ranko Scepanovic , Alexander E. Andreev , Ivan Pavisic
发明人： Ranko Scepanovic , Alexander E. Andreev , Ivan Pavisic
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method for maximizing effectiveness of parallel processing, using multiple processors, to achieve an optimal cell placement layout on an integrated circuit (IC) chip is disclosed. The method requires the cells of the IC to be assigned to one of the multiple processors in a manner to balance the work load among the multiple processors. Then, the affinity of the cells to each of the multiple processors is determined. The affinity of the cells, including the conflict reduction factors and work load balancing factors, is used to reassign the cells to the processors. The cell affinity calculation and the processor reassignment are repeated until no cells are reassigned or for a fixed number of times. The assignment of the cells to the multiple processors and subsequent reassignments of the cells based on affinity of the cells to the processors reduces or eliminates the problems associated with prior parallel cell placement techniques.
摘要翻译：公开了一种用于最大化使用多个处理器的并行处理的有效性以在集成电路（IC）芯片上实现最佳单元布局布局的方法。该方法要求以多个处理器之间的工作负载平衡的方式将IC的单元分配给多个处理器之一。然后，确定小区对多个处理器中的每一个的亲和性。使用包括冲突减少因子和工作负载均衡因素在内的小区的亲和性将这些小区重新分配给处理器。重复细胞亲和度计算和处理器重新分配，直到没有细胞被重新分配或固定次数为止。基于小区对处理器的亲和性的将小区分配给多个处理器和随后的小区重新分配减少或消除与先前的并行小区布置技术相关的问题。

20. 发明授权

US08566769B2 Method and apparatus for generating memory models and timing database 失效
标题翻译：用于生成内存模型和计时数据库的方法和装置
公开(公告)号：US08566769B2
公开(公告)日：2013-10-22
申请号：US13547884
申请日：2012-07-12
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

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