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11. 发明授权

US07342673B2 Device for defining participants of a control system for a printing machine 有权
标题翻译：用于定义印刷机控制系统参与者的装置
公开(公告)号：US07342673B2
公开(公告)日：2008-03-11
申请号：US10006580
申请日：2001-12-04
申请人： Ulrich Grimm , Silke Husterer , Thomas Husterer , Georg Roessler , Andreas Wagner
发明人： Ulrich Grimm , Silke Husterer , Thomas Husterer , Georg Roessler , Andreas Wagner
IPC分类号： G06F15/00
CPC分类号： H01R29/00 , B41F33/0009
摘要： A device for defining participants in a control system that controls a printing machine is provided. The control system includes a central computer and a number of participants which interact with the central computer in order to carry out processes. The participants are connected to one another via lines of a bus system. The lines of the bus system and the participants have respective plugs for connecting the lines of the bus system to the participants. The plugs of the lines of the bus system have reserved plug contacts which are provided with one or more galvanic links for defining the respective participants.
摘要翻译：提供了一种用于定义控制打印机的控制系统中的参与者的装置。控制系统包括中央计算机和与中央计算机交互以执行处理的多个参与者。参与者通过总线系统的线路相互连接。总线系统和参与者的线路具有用于将总线系统的线路连接到参与者的相应插头。总线系统的线路的插头具有预留的插头触点，其具有用于限定相应参与者的一个或多个电气连接。

12. 发明申请

US20080031935A1 Cholinesterase Inhibitors In Liposomes And Their Production And Use 审中-公开
标题翻译：胆碱酯酶抑制剂在脂质体及其生产和使用
公开(公告)号：US20080031935A1
公开(公告)日：2008-02-07
申请号：US11578191
申请日：2005-04-21
申请人： Angelika Bodenteich , Josef Bockmann , Werner Frantsits , Eberhard Pirich , Andreas Wagner , Karola Vorauer-Uhl
发明人： Angelika Bodenteich , Josef Bockmann , Werner Frantsits , Eberhard Pirich , Andreas Wagner , Karola Vorauer-Uhl
IPC分类号： A61K9/127 , A61K31/27 , A61K31/407 , A61K31/435 , A61P25/00 , A61K31/4353 , A61K31/55 , A61K31/661
CPC分类号： A61K9/127
摘要： The invention relates to a pharmaceutical composition based on an active ingredient that is enclosed in liposomes for topical, transdermal application. The interior of said liposomes comprises an acidic, aqueous medium containing at least one cholinesterase inhibitor, preferably from the group containing donepezil, rivastigmine, galantamine, physostigmine, heptylphysostigmine, phenserine, tolserine, cymserine, thiatolserine, thiacymserine, neostigmine, huperzine, tacrine, metrifonate and dichlorvos, or an enantiomer or derivative of at least one of said compounds. In addition, the invention relates to a method for producing said composition, optionally in a sterile form and also to the use of the liposomes charged with the active ingredient in various galenic formulations for topical, transdermal application with a depot effect in the epidermis, for the prophylaxis and/or treatment of cutaneous neuropathic pain or the loss of cutaneous sensory function as a result of neuropathy.
摘要翻译：本发明涉及一种基于活性成分的药物组合物，其被包封在用于局部，经皮施用的脂质体中。所述脂质体的内部包含含有至少一种胆碱酯酶抑制剂的酸性水性培养基，优选来自含有多奈哌齐，利凡斯的明，加兰他敏，毒扁豆碱，庚基苯非司明，苯丝氨酸，丝氨酸，胞嘧磺酸，硫蛋白丝氨酸，硫柳汞，新斯的明，石杉碱，他克林，和二氯葡聚糖，或至少一种所述化合物的对映异构体或衍生物。此外，本发明涉及任选地以无菌形式生产所述组合物的方法，还涉及在各种盖仑制剂中装载活性成分的脂质体用于在表皮中具有贮库作用的局部，经皮施用的用途，预防和/或治疗皮肤神经性疼痛或神经病变导致皮肤感觉功能丧失。

13. 发明授权

US07308592B2 Redundant oscillator distribution in a multi-processor server system 失效
标题翻译：多处理器服务器系统中的冗余振荡器分布
公开(公告)号：US07308592B2
公开(公告)日：2007-12-11
申请号：US11056009
申请日：2005-02-11
申请人： Dietmar Schmunkamp , Andreas Wagner , Tobias Webel , Ulrich Weiss
发明人： Dietmar Schmunkamp , Andreas Wagner , Tobias Webel , Ulrich Weiss
IPC分类号： G06F1/12 , G06F13/42 , H04L5/00
CPC分类号： G06F11/1604 , G06F11/20
摘要： The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. More redundancy even to the Dynamic Clock Switching Circuit (DCSC) (14) and the wiring (17) from there to multiple, PLL-(12) free clock chips (22) is provided. Instead of only one DCSC (14) and one single wiring (17), two of them (14-0, 14-1; 17-0, 17-1) are used combined with a further particular logic present on each clock chip (22), which in combination generate two synchronous, fine-tuned, minimum-shifted clock signals and select always the first of them to arrive at a FlipFlop controlling the output for clock distribution wiring.
摘要翻译：本发明涉及计算机系统中的系统时钟。特别地，它涉及具有增强的性能和可靠性程度的高端多处理器，多节点服务器计算机系统中的系统时钟以及用于在第一和第二时钟信号之间动态切换的方法，如果第一应用失败。提供了更多的冗余，即使是动态时钟切换电路（DCSC）（14）和布线（17），也可以是多个PLL-（12）空闲时钟芯片（22）。而不是只有一个DCSC（14）和一个单个布线（17），它们中的两个（14 - 0，14 - 1，17 - 0，17 - 1）与每个时钟芯片上存在的另一个特定逻辑 22），其组合产生两个同步，微调的最小移位时钟信号，并总是选择第一个来获得控制时钟分配布线输出的FlipFlop。

14. 发明授权

US07278303B2 Method for diagnosing an engine control unit and corresponding engine control unit 有权
标题翻译：用于诊断发动机控制单元和相应的发动机控制单元的方法
公开(公告)号：US07278303B2
公开(公告)日：2007-10-09
申请号：US11243782
申请日：2005-10-05
申请人： Jan Piewek , Jens Jeschke , Andreas Wagner , Thomas Lang
发明人： Jan Piewek , Jens Jeschke , Andreas Wagner , Thomas Lang
IPC分类号： G01M15/00
CPC分类号： F02D35/023 , F02D41/222 , Y02T10/40
摘要： A method for diagnosing an engine control unit (4) conducts an analysis as to whether the signal values from the cylinder pressure sensors (3) are faulty based on at least one characteristic value which is derived from an evaluation of signal values from the cylinder pressure sensors (3) of the cylinders (2) in a combustion engine (5). In addition to this is described the engine control unit (4) designed to execute the method. Also hereby disclosed is a method which, based on symmetrical aspects, determines a crankshaft angle (phipCylMaxTDC) for a cylinder pressure maximum during push mode operation of the combustion engine (5).
摘要翻译：用于诊断发动机控制单元（4）的方法基于从来自气缸压力的信号值的评估导出的至少一个特性值来进行来自气缸压力传感器（3）的信号值是否有故障的分析内燃机（5）中气缸（2）的传感器（3）。除此之外，还描述了设计用于执行该方法的发动机控制单元（4）。此外，还公开了一种基于对称方面的方法，其确定在内燃机（5）的推压模式操作期间的气缸最大压力的曲轴角度（phipCylMaxTDC）。

15. 发明授权

US07124032B2 System and method for reconstructing pathways in large genetic networks from genetic perturbations 失效
公开(公告)号：US07124032B2
公开(公告)日：2006-10-17
申请号：US10140323
申请日：2002-05-07
申请人： Andreas Wagner
发明人： Andreas Wagner
IPC分类号： G01N33/48 , G06F19/00
CPC分类号： G06F19/12
摘要： A system and method for reconstructing pathways in large genetic networks from genetic perturbations comprises an analysis method and system that applies a recursive algorithm for determining the path between every gene pair in an arbitrarily large genetic network from large-scale gene perturbation data and reconstructs all direct and indirect regulatory gene interactions in the network. Graph theory mathematics is applied to genetic network reconstruction in the following manner: Genetic perturbation data is used to identify all genes accessible from a perturbed gene to generate an accessibility list for the gene. Graph theory mathematics is applied to the accessibility list and its graph to determine a condensation of the graph as defined by the condensation's accessibility list. Graph theory mathematics is applied to the accessibility list, such as through a recursive algorithm performed on a desktop computer, to obtain an adjacency list for the gene that characterizes a genetic network.

16. 发明授权

US06948085B2 Method and device for synchronizing processes which are performed on a plurality of units 有权
标题翻译：用于同步在多个单元上执行的处理的方法和装置
公开(公告)号：US06948085B2
公开(公告)日：2005-09-20
申请号：US09997981
申请日：2001-11-29
申请人： Kai Albrecht , Ulrich Grimm , Thomas Husterer , Reinhard Janzer , Helmut Meyer , Georg Roessler , Andreas Wagner
发明人： Kai Albrecht , Ulrich Grimm , Thomas Husterer , Reinhard Janzer , Helmut Meyer , Georg Roessler , Andreas Wagner
IPC分类号： G06F1/12 , B41F33/00 , G04G7/00 , G05B15/02 , G06F1/10
CPC分类号： G04G7/00 , B41F33/00
摘要： A device for synchronizing processes which run on a plurality of units including a central unit linked with other units via a field bus, includes a device provided in the central unit for producing a system clock, the field bus having a vacant line for distributing the system clock to the other units, and respective multiplication devices located at the other units for multiplying the system clock; and a method of operating the device for synchronizing processes.
摘要翻译：一种用于同步在包括与其他单元经由现场总线连接的中央单元的多个单元上运行的处理的设备包括设置在中央单元中用于产生系统时钟的设备，该现场总线具有用于分配系统的空行时钟到其他单元，以及位于其他单元的相应乘法装置，用于乘法系统时钟; 以及操作用于同步过程的设备的方法。

17. 发明授权

US08955702B2 Luffing-jib tower crane with jib angle error control 有权
标题翻译：起重臂起重机起重臂起偏角控制
公开(公告)号：US08955702B2
公开(公告)日：2015-02-17
申请号：US13578951
申请日：2011-02-16
申请人： Andreas Wagner
发明人： Andreas Wagner
IPC分类号： B66C13/16 , B66C23/88 , B66C23/82
CPC分类号： B66C23/88 , B66C23/82
摘要： A luffing-jib tower crane, comprising a tower and a jib which is connected to the tower via a joint and is held by a luffing cable, wherein the length of the luffing cable can be changed by a drawing-in unit, by the luffing cable being wound onto or unwound from a cable drum of the drawing-in unit, wherein the angle of the jib with respect to the horizontal plane is measured by a first sensor winch is attached to the jib (first angular value), wherein a measuring device measures the length of the unwound part of the luffing cable, from which length the minimum angle of the jib with respect to the horizontal plane (second angular value) can be calculated, and the first angular value can be compared with the second angular value.
摘要翻译：一种起重臂起重机，包括塔架和起重臂，其通过接头连接到塔架并且由变幅缆绳保持，其中变幅缆线的长度可以通过牵引单元通过变幅电缆从牵引单元的电缆卷筒卷绕或退绕，其中，起重臂相对于水平面的角度由第一传感器绞盘测量，附接到起重臂（第一角度值），其中测量装置测量变幅电缆的退绕部分的长度，从该长度可以计算起重臂相对于水平面的最小角度（第二角度值），并且可以将第一角度值与第二角度值进行比较。

18. 发明授权

US07913140B2 Method and device to detect failure of static control signals 失效
标题翻译：检测静态控制信号故障的方法和装置
公开(公告)号：US07913140B2
公开(公告)日：2011-03-22
申请号：US12174621
申请日：2008-07-16
申请人： Matthias Klein , Andreas Wagner , Gerhard Zilles , Manfred H Walz , Thomas Buechner
发明人： Matthias Klein , Andreas Wagner , Gerhard Zilles , Manfred H Walz , Thomas Buechner
IPC分类号： G01R31/28
CPC分类号： G01R31/3177
摘要： A method and circuits for monitoring and detecting an error in the static pervasive signals applied to input/output pins of an integrated circuit during functional operation of the integrated circuit. The method and circuits provide a signal signature of each of one or more groups of the static pervasive signals and then monitoring the signal signature for any change of logic level.
摘要翻译：一种用于在集成电路的功能操作期间监视和检测施加到集成电路的输入/输出引脚的静态普及信号中的误差的方法和电路。该方法和电路提供静态普遍信号的一个或多个组中的每一个的信号签名，然后监视逻辑电平的任何改变的信号签名。

19. 发明申请

US20090288046A1 CIRCUIT DESIGN PROCESSES 有权
标题翻译：电路设计流程
公开(公告)号：US20090288046A1
公开(公告)日：2009-11-19
申请号：US12122785
申请日：2008-05-19
申请人： Rainer Dorsch , Marta Junginger , Philipp Salz , Andreas Wagner , Gerhard Zilles
发明人： Rainer Dorsch , Marta Junginger , Philipp Salz , Andreas Wagner , Gerhard Zilles
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/14
摘要： A method for designing a circuit. The method includes (i) providing a netlist of a design and (ii) dividing the netlist into N user logics, N being a positive integer. After said dividing the netlist is performed, the N user logics in N macro test wrappers are instantiated resulting in N instantiated logics. After said instantiating the N user logics is performed, the N instantiated logics are processed. After said processing is performed, a result of said processing is back-annotated to the netlist.
摘要翻译：一种设计电路的方法。该方法包括（i）提供设计的网表，（ii）将网表划分为N个用户逻辑，N是正整数。在划分网表后，N个宏测试包装器中的N个用户逻辑被实例化，导致N个实例化的逻辑。在实例化N个用户逻辑之后，处理N个实例化的逻辑。在执行所述处理之后，将所述处理的结果反向注释到网表。

20. 发明申请

US20060184814A1 Redundant oscillator distribution in a multi-processor server system 失效
标题翻译：多处理器服务器系统中的冗余振荡器分布
公开(公告)号：US20060184814A1
公开(公告)日：2006-08-17
申请号：US11056009
申请日：2005-02-11
申请人： Dietmar Schmunkamp , Andreas Wagner , Tobias Webel , Ulrich Weiss
发明人： Dietmar Schmunkamp , Andreas Wagner , Tobias Webel , Ulrich Weiss
IPC分类号： G06F1/06
CPC分类号： G06F11/1604 , G06F11/20
摘要： The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. More redundancy even to the Dynamic Clock Switching Circuit (DCSC) (14) and the wiring (17) from there to multiple, PLL-(12) free clock chips (22) is provided. Instead of only one DCSC (14) and one single wiring (17), two of them (14-0, 14-1; 17-0, 17-1) are used combined with a further particular logic present on each clock chip (22), which in combination generate two synchronous, fine-tuned, minimum-shifted clock signals and select always the first of them to arrive at a FlipFlop controlling the output for clock distribution wiring.
摘要翻译：本发明涉及计算机系统中的系统时钟。特别地，它涉及具有增强的性能和可靠性程度的高端多处理器，多节点服务器计算机系统中的系统时钟以及用于在第一和第二时钟信号之间动态切换的方法，如果第一应用失败。提供了更多的冗余，即使是动态时钟切换电路（DCSC）（14）和布线（17），也可以是多个PLL-（12）空闲时钟芯片（22）。而不是只有一个DCSC（14）和一个单个布线（17），它们中的两个（14 - 0，14 - 1，17 - 0，17 - 1）与每个时钟芯片上存在的另一个特定逻辑 22），其组合产生两个同步，微调的最小移位时钟信号，并总是选择第一个来获得控制时钟分配布线输出的FlipFlop。

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