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11. 发明申请

US20140035066A1 Non-Planar FET and Manufacturing Method Thereof 有权
标题翻译：非平面FET及其制造方法
公开(公告)号：US20140035066A1
公开(公告)日：2014-02-06
申请号：US13562322
申请日：2012-07-31
申请人： Shih-Hung Tsai , Ssu-I Fu , Ying-Tsung Chen , Chih-Wei Chen , Ying-Chih Lin , Chien-Ting Lin , Hsuan-Hsu Chen
发明人： Shih-Hung Tsai , Ssu-I Fu , Ying-Tsung Chen , Chih-Wei Chen , Ying-Chih Lin , Chien-Ting Lin , Hsuan-Hsu Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/51 , H01L29/66818 , H01L29/785
摘要： The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.
摘要翻译：本发明提供一种非平面FET，其包括基板，鳍结构，子间隔物，栅极，电介质层和源极/漏极区域。翅片结构设置在基板上。子间隔件仅设置在翅片结构的中间侧壁上。门设置在翅片结构上。介电层设置在翅片结构和栅极之间。源/漏区设置在鳍结构中。本发明还提供一种形成该方法的方法。

12. 发明授权

US08872280B2 Non-planar FET and manufacturing method thereof 有权
标题翻译：非平面FET及其制造方法
公开(公告)号：US08872280B2
公开(公告)日：2014-10-28
申请号：US13562322
申请日：2012-07-31
申请人： Shih-Hung Tsai , Ssu-I Fu , Ying-Tsung Chen , Chih-Wei Chen , Ying-Chih Lin , Chien-Ting Lin , Hsuan-Hsu Chen
发明人： Shih-Hung Tsai , Ssu-I Fu , Ying-Tsung Chen , Chih-Wei Chen , Ying-Chih Lin , Chien-Ting Lin , Hsuan-Hsu Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/66795 , H01L29/51 , H01L29/66818 , H01L29/785
摘要： The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.
摘要翻译：本发明提供一种非平面FET，其包括基板，鳍结构，子间隔物，栅极，电介质层和源极/漏极区域。翅片结构设置在基板上。子间隔件仅设置在翅片结构的中间侧壁上。门设置在翅片结构上。介电层设置在翅片结构和栅极之间。源/漏区设置在鳍结构中。本发明还提供一种形成该方法的方法。

13. 发明授权

US08722501B2 Method for manufacturing multi-gate transistor device 有权
标题翻译：多栅极晶体管器件制造方法
公开(公告)号：US08722501B2
公开(公告)日：2014-05-13
申请号：US13275337
申请日：2011-10-18
申请人： Shih-Hung Tsai , Chien-Liang Lin , Chien-Ting Lin , Ssu-I Fu , Ying-Tsung Chen
发明人： Shih-Hung Tsai , Chien-Liang Lin , Chien-Ting Lin , Ssu-I Fu , Ying-Tsung Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/66795
摘要： A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer.
摘要翻译：一种制造多栅极晶体管器件的方法包括：提供具有图案化半导体层，栅极电介质层和顺序地形成在其上的栅极层的半导体衬底，形成依次具有第一绝缘层和第二绝缘层的覆盖层图案化半导体层和栅极层，去除多个绝缘层的一部分以同时在栅极层周围形成第一间隔物，以及围绕图案化半导体层形成第二间隔物，去除第二间隔物以暴露第一绝缘层的一部分覆盖图案化的半导体层并且同时移除第一间隔物的一部分以形成围绕栅极层的第三间隔物，以及去除暴露的第一绝缘层以暴露图案化的半导体层。

14. 发明申请

US20130095616A1 METHOD FOR MANUFACTURING MULTI-GATE TRANSISTOR DEVICE 有权
标题翻译：制造多栅极晶体管器件的方法
公开(公告)号：US20130095616A1
公开(公告)日：2013-04-18
申请号：US13275337
申请日：2011-10-18
申请人： Shih-Hung Tsai , Chien-Liang Lin , Chien-Ting Lin , Ssu-I Fu , Ying-Tsung Chen
发明人： Shih-Hung Tsai , Chien-Liang Lin , Chien-Ting Lin , Ssu-I Fu , Ying-Tsung Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/66795
摘要： A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer.
摘要翻译：一种制造多栅极晶体管器件的方法包括：提供具有图案化半导体层，栅极电介质层和顺序地形成在其上的栅极层的半导体衬底，形成依次具有第一绝缘层和第二绝缘层的覆盖层图案化半导体层和栅极层，去除多个绝缘层的一部分以同时在栅极层周围形成第一间隔物，以及围绕图案化半导体层形成第二间隔物，去除第二间隔物以暴露第一绝缘层的一部分覆盖图案化的半导体层并且同时移除第一间隔物的一部分以形成围绕栅极层的第三间隔物，以及去除暴露的第一绝缘层以暴露图案化的半导体层。

15. 发明申请

US20140015056A1 MULTI-GATE MOSFET AND PROCESS THEREOF 有权
标题翻译：多栅MOSFET及其工艺
公开(公告)号：US20140015056A1
公开(公告)日：2014-01-16
申请号：US13545967
申请日：2012-07-10
申请人： Ssu-I Fu , En-Chiuan Liou , Chih-Wei Yang , Ying-Tsung Chen , Shih-Hung Tsai
发明人： Ssu-I Fu , En-Chiuan Liou , Chih-Wei Yang , Ying-Tsung Chen , Shih-Hung Tsai
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/785
摘要： A multi-gate MOSFET includes a substrate, a dielectric layer and at least a fin-shaped structure. The substrate has a first area and a second area. The dielectric layer is only located in the substrate of the first area. At least a fin-shaped structure is located on the dielectric layer. Moreover, the present invention also provides a multi-gate MOSFET process forming said multi-gate MOSFET.
摘要翻译：多栅极MOSFET包括衬底，电介质层和至少鳍状结构。衬底具有第一区域和第二区域。电介质层仅位于第一区域的衬底中。至少一个鳍状结构位于介电层上。此外，本发明还提供一种形成所述多栅极MOSFET的多栅极MOSFET工艺。

16. 发明授权

US09269791B2 Multi-gate MOSFET with embedded isolation structures 有权
标题翻译：具有嵌入式隔离结构的多栅极MOSFET
公开(公告)号：US09269791B2
公开(公告)日：2016-02-23
申请号：US13545967
申请日：2012-07-10
申请人： Ssu-I Fu , En-Chiuan Liou , Chih-Wei Yang , Ying-Tsung Chen , Shih-Hung Tsai
发明人： Ssu-I Fu , En-Chiuan Liou , Chih-Wei Yang , Ying-Tsung Chen , Shih-Hung Tsai
IPC分类号： H01L27/088 , H01L29/66 , H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/785
摘要： A multi-gate MOSFET includes a substrate, a dielectric layer and at least a fin-shaped structure. The substrate has a first area and a second area. The dielectric layer is only located in the substrate of the first area. At least a fin-shaped structure is located on the dielectric layer. Moreover, the present invention also provides a multi-gate MOSFET process forming said multi-gate MOSFET.
摘要翻译：多栅极MOSFET包括衬底，电介质层和至少鳍状结构。衬底具有第一区域和第二区域。电介质层仅位于第一区域的衬底中。至少一个鳍状结构位于介电层上。此外，本发明还提供一种形成所述多栅极MOSFET的多栅极MOSFET工艺。

17. 发明授权

US09384962B2 Oxygen treatment of replacement work-function metals in CMOS transistor gates 有权
标题翻译： CMOS晶体管栅极中替代工作功能金属的氧化处理
公开(公告)号：US09384962B2
公开(公告)日：2016-07-05
申请号：US13082387
申请日：2011-04-07
申请人： Guang-Yaw Hwang , Chun-Hsien Lin , Hung-Ling Shih , Jiunn-Hsiung Liao , Zhi-Cheng Lee , Shao-Hua Hsu , Yi-Wen Chen , Cheng-Guo Chen , Jung-Tsung Tseng , Chien-Ting Lin , Tong-Jyun Huang , Jie-Ning Yang , Tsung-Lung Tsai , Po-Jui Liao , Chien-Ming Lai , Ying-Tsung Chen , Cheng-Yu Ma , Wen-Han Hung , Che-Hua Hsu
发明人： Guang-Yaw Hwang , Chun-Hsien Lin , Hung-Ling Shih , Jiunn-Hsiung Liao , Zhi-Cheng Lee , Shao-Hua Hsu , Yi-Wen Chen , Cheng-Guo Chen , Jung-Tsung Tseng , Chien-Ting Lin , Tong-Jyun Huang , Jie-Ning Yang , Tsung-Lung Tsai , Po-Jui Liao , Chien-Ming Lai , Ying-Tsung Chen , Cheng-Yu Ma , Wen-Han Hung , Che-Hua Hsu
IPC分类号： H01L21/28 , H01L21/02
CPC分类号： H01L29/517 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7845 , H01L29/7846
摘要： A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.
摘要翻译：提供一种制造金属栅极的方法。该方法包括提供基板。然后，在基板上形成栅极电介质层。在栅极电介质层上形成具有功函数金属层的多层堆叠结构。在多层堆叠结构的至少一层上进行O2气氛处理。在多层堆叠结构上形成导电层。

18. 发明申请

US20120256276A1 Metal Gate and Fabricating Method Thereof 有权
标题翻译：金属门及其制造方法
公开(公告)号：US20120256276A1
公开(公告)日：2012-10-11
申请号：US13082387
申请日：2011-04-07
申请人： Guang-Yaw Hwang , Chun-Hsien Lin , Hung-Ling Shih , Jiunn-Hsiung Liao , Zhi-Cheng Lee , Shao-Hua Hsu , Yi-Wen Chen , Cheng-Guo Chen , Jung-Tsung Tseng , Chien-Ting Lin , Tong-Jyun Huang , Jie-Ning Yang , Tsung-Lung Tsai , Po-Jui Liao , Chien-Ming Lai , Ying-Tsung Chen , Cheng-Yu Ma , Wen-Han Hung , Che-Hua Hsu
发明人： Guang-Yaw Hwang , Chun-Hsien Lin , Hung-Ling Shih , Jiunn-Hsiung Liao , Zhi-Cheng Lee , Shao-Hua Hsu , Yi-Wen Chen , Cheng-Guo Chen , Jung-Tsung Tseng , Chien-Ting Lin , Tong-Jyun Huang , Jie-Ning Yang , Tsung-Lung Tsai , Po-Jui Liao , Chien-Ming Lai , Ying-Tsung Chen , Cheng-Yu Ma , Wen-Han Hung , Che-Hua Hsu
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L29/517 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7845 , H01L29/7846
摘要： A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.
摘要翻译：提供一种制造金属栅极的方法。该方法包括提供基板。然后，在基板上形成栅极电介质层。在栅极电介质层上形成具有功函数金属层的多层堆叠结构。在多层堆叠结构的至少一层上进行O2气氛处理。在多层堆叠结构上形成导电层。

19. 发明授权

US08975179B2 Planarization process for semiconductor device fabrication 有权
标题翻译：半导体器件制造的平面化过程
公开(公告)号：US08975179B2
公开(公告)日：2015-03-10
申请号：US13275962
申请日：2011-10-18
申请人： Che-Hao Tu , Weilun Hong , Ying-Tsung Chen , Liang-Guang Chen
发明人： Che-Hao Tu , Weilun Hong , Ying-Tsung Chen , Liang-Guang Chen
IPC分类号： H01L21/4763 , H01L21/3105 , H01L29/66 , H01L21/28 , H01L29/51
CPC分类号： H01L21/31053 , H01L21/28079 , H01L21/28088 , H01L29/517 , H01L29/66545
摘要： The present disclosure provides a method of semiconductor fabrication including forming a dielectric layer is formed on and interposing a first feature and a second feature. A first CMP process is performed on the dielectric layer to removing the dielectric layer from a top surface of the first feature to expose an underlying layer and decreasing a thickness of the dielectric layer disposed on a top surface of the second feature such that a portion of the dielectric layer remains disposed on the top surface of the second feature. Thereafter, a second CMP process is performed which removes the dielectric layer remaining on the top surface of the second feature.
摘要翻译：本公开提供了一种半导体制造方法，包括形成介电层，并形成第一特征和第二特征。在电介质层上执行第一CMP工艺以从第一特征的顶表面去除电介质层以暴露下层，并减小设置在第二特征的顶表面上的介电层的厚度，使得电介质层保持设置在第二特征的顶表面上。此后，进行第二CMP处理，其移除残留在第二特征的顶表面上的电介质层。

20. 发明授权

US6037260A Polishing composition 失效
标题翻译：抛光组成
公开(公告)号：US6037260A
公开(公告)日：2000-03-14
申请号：US76116
申请日：1998-05-12
申请人： Ming-Shyong Tsai , Li-Mei Chen , Yue-Chin Yeh , Chiu-Chih Hsieh , Ying-Tsung Chen
发明人： Ming-Shyong Tsai , Li-Mei Chen , Yue-Chin Yeh , Chiu-Chih Hsieh , Ying-Tsung Chen
IPC分类号： C09G1/02 , C09K3/14 , H01L21/304 , C07K13/00
CPC分类号： C09G1/02 , C09K3/1463 , Y10T29/47
摘要： The present invention provides a polishing composition which comprises 100 weight part of water; 0.5 to 20 weight part of boehmite, a hydroxide of aluminum, pseudoboehmite or mixtures thereof; 1 to 50 weight part of aluminum oxide (Al.sub.2 O.sub.3); and 1 to 20 weight part of an acidic solution. The polishing composition of the present invention is a thixotropic fluid and displays satisfactory suspension properties. Therefore, it is very suitable for use as a polishing slurry.
摘要翻译：本发明提供一种抛光组合物，其包含100重量份的水; 勃姆石0.5〜20重量份，铝氢氧化物，假勃姆石或其混合物; 1〜50重量份的氧化铝（Al2O3）; 和1〜20重量份的酸性溶液。本发明的研磨用组合物是触变性液体，显示出令人满意的悬浮性。因此，非常适合用作研磨浆料。

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