专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US06455938B1 Integrated circuit interconnect shunt layer 有权
标题翻译：集成电路互连分流层
公开(公告)号：US06455938B1
公开(公告)日：2002-09-24
申请号：US09905479
申请日：2001-07-13
申请人： Pin-Chin Connie Wang , Amit P. Marathe , Christy Mei-Chu Woo
发明人： Pin-Chin Connie Wang , Amit P. Marathe , Christy Mei-Chu Woo
IPC分类号： H01L2945
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided for an integrated circuit on a semiconductor substrate grated circuit having a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the opening, and a first conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A shunt layer is in the via opening above the conductor core. A barrier layer lines the second channel and via opening over the shunt layer and the second dielectric layer. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via.
摘要翻译：提供了一种用于具有半导体器件的半导体衬底格栅电路上的集成电路的集成电路及其制造方法。电介质层位于半导体衬底上，其中设有开口。阻挡层对开口进行排列，并且第一导体芯填充阻挡层上的开口。第二电介质层形成在第一电介质层上并具有设置在其中的第二通道和通孔。并联层位于导体芯上方的通孔中。阻挡层将第二通道和通过开口穿过并联层和第二介电层。导体芯填充第二通道并通过阻挡层和第一导体芯上的开口形成第二通道和通孔。

12. 发明授权

US06417566B1 Void eliminating seed layer and conductor core integrated circuit interconnects 有权
标题翻译：消除种子层和导体芯集成电路互连
公开(公告)号：US06417566B1
公开(公告)日：2002-07-09
申请号：US09705121
申请日：2000-11-01
申请人： Pin-Chin Connie Wang , Amit P. Marathe
发明人： Pin-Chin Connie Wang , Amit P. Marathe
IPC分类号： H01L2348
CPC分类号： H01L21/76873 , H01L21/76843 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. A seed layer is disposed between the barrier layer and the conductor core. The seed layer has an associated element which is formed during annealing into an intermetallic compound which has a density lower than the density of the conductor core.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。在半导体衬底上形成器件电介质层，器件电介质层上的沟道电介质层上形成有开口。阻挡层对通道开口进行排列，并且导体芯填充阻挡层上的开口。种子层设置在阻挡层和导体芯之间。种子层具有在退火成形成密度低于导体芯的密度的金属间化合物的相关元件。

13. 发明授权

US06861349B1 Method of forming an adhesion layer with an element reactive with a barrier layer 失效
标题翻译：用与阻挡层反应的元件形成粘合层的方法
公开(公告)号：US06861349B1
公开(公告)日：2005-03-01
申请号：US10145944
申请日：2002-05-15
申请人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76859 , H01L21/76873 , H01L21/76874
摘要： A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into an interfacial layer over the barrier material layer, depositing an alloy layer over the interfacial layer. The implanted first alloy element is reactive with the barrier material layer to increase resistance to copper diffusion.
摘要翻译：一种制造集成电路的方法可以包括沿着侧壁和形成通孔的底部形成阻挡材料层，所述通孔被配置为接收电连接第一导电层和第二导电层的通孔材料，注入第一合金元素进入阻挡材料层上的界面层，在界面层上沉积合金层。植入的第一合金元素与阻挡材料层反应，以增加对铜扩散的抗性。

14. 发明授权

US06657303B1 Integrated circuit with low solubility metal-conductor interconnect cap 有权
标题翻译：具有低溶解度金属导体互连帽的集成电路
公开(公告)号：US06657303B1
公开(公告)日：2003-12-02
申请号：US10016024
申请日：2001-12-12
申请人： Pin-Chin Connie Wang , Steven C. Avanzino
发明人： Pin-Chin Connie Wang , Steven C. Avanzino
IPC分类号： H01L3900
CPC分类号： H01L21/76849 , H01L21/76855 , H01L21/76858 , H01L21/76862 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A cerium-conductor interconnect cap is disposed over the conductor core with a capping layer over the dielectric layer and the cerium-conductor interconnect cap.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。形成在半导体衬底上的器件电介质层。器件电介质层上的沟道介电层具有形成在其中的开口。屏障层对通道开口进行排列。导体芯填充阻挡层上的开口。铈导体互连帽设置在导电芯上方，在电介质层和铈导体互连帽上方具有覆盖层。

15. 发明授权

US06534865B1 Method of enhanced fill of vias and trenches 有权
标题翻译：增强通孔和沟槽填充的方法
公开(公告)号：US06534865B1
公开(公告)日：2003-03-18
申请号：US09880219
申请日：2001-06-12
申请人： Sergey D. Lopatin , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Pin-Chin Connie Wang
IPC分类号： H01L21321
CPC分类号： H01L23/5226 , C23C18/1605 , C25D5/02 , H01L21/3212 , H01L21/76843 , H01L21/76847 , H01L21/76859 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76879 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method and apparatus for filling vias and trenches in integrated circuits is provided having a substrate with a device provided thereon. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening provided therein. A barrier layer lines the opening of the channel dielectric. A seed layer is deposited over the barrier layer. Portions of the seed layer are then doped with a material that inhibits the deposition of copper by electroplating or electroless deposition using ion implantation. A conductor core layer is deposited on the seed layer by electroplating or electroless deposition, filling the opening over the barrier layer. The inhibiting material on the doped seed layer creates a filling profile that allows for a more efficient, faster, void-free filling of the conductor core layer.
摘要翻译：提供一种用于在集成电路中填充过孔和沟槽的制造方法和装置，其具有设置在其上的装置的基板。在半导体衬底上形成器件电介质层。器件电介质层上的沟道电介质层具有设置在其中的开口。阻挡层对通道电介质的开口进行排列。种子层沉积在阻挡层上。然后通过使用离子注入的电镀或无电沉积来抑制铜的沉积的材料掺杂种子层的部分。通过电镀或无电沉积将导体芯层沉积在种子层上，填充阻挡层上的开口。掺杂种子层上的抑制材料产生填充轮廓，其允许导体芯层更有效，更快速，无空隙的填充。

16. 发明授权

US07169706B2 Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition 失效
标题翻译：使用化学气相沉积（CVD）铜沉积的粘附前体层的方法
公开(公告)号：US07169706B2
公开(公告)日：2007-01-30
申请号：US10687186
申请日：2003-10-16
申请人： Sergey D. Lopatin , Paul R. Besser , Alline F. Myers , Jeremias D. Romero , Minh Q. Tran , Lu You , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Paul R. Besser , Alline F. Myers , Jeremias D. Romero , Minh Q. Tran , Lu You , Pin-Chin Connie Wang
IPC分类号： H01L21/44
CPC分类号： H01L21/76846 , H01L21/76877
摘要： An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.
摘要翻译：示例性实施例涉及在集成电路制造工艺中使用粘附前体的方法。该方法包括在介电材料上提供材料的气体并在粘附前体层上提供铜层。粘附前体层由气体形成，电介质材料包括孔。

17. 发明授权

US06992004B1 Implanted barrier layer to improve line reliability and method of forming same 有权
标题翻译：植入障碍层提高线路可靠性及其形成方法
公开(公告)号：US06992004B1
公开(公告)日：2006-01-31
申请号：US10209060
申请日：2002-07-31
申请人： Paul R. Besser , Matthew S. Buynoski , Minh Q. Tran , Pin-Chin Connie Wang , Lu You , Sergey D. Lopatin , Jeremias D. Romero
发明人： Paul R. Besser , Matthew S. Buynoski , Minh Q. Tran , Pin-Chin Connie Wang , Lu You , Sergey D. Lopatin , Jeremias D. Romero
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76801 , H01L21/76829 , H01L21/76834 , H01L21/76849 , H01L21/76858 , H01L21/76859 , H01L21/76867
摘要： A method for manufacturing an integrated circuit having improved electromigration characteristics includes forming an aperture in an interlevel dielectric layer and providing a barrier layer in the aperture. The aperture is filled with a metal material and a barrier layer is provided above the metal material. An intermetallic region can be formed at an interface of the metal material and the barrier layer. The intermetallic material can be formed by implantation of species.
摘要翻译：用于制造具有改善的电迁移特性的集成电路的方法包括在层间电介质层中形成孔，并在孔中提供阻挡层。孔被金属材料填充，并且在金属材料上方设有阻挡层。可以在金属材料和阻挡层的界面处形成金属间化合物区域。金属间化合物可以通过种植物形成。

18. 发明授权

US06656836B1 Method of performing a two stage anneal in the formation of an alloy interconnect 有权
标题翻译：在形成合金互连件时执行两阶段退火的方法
公开(公告)号：US06656836B1
公开(公告)日：2003-12-02
申请号：US10100395
申请日：2002-03-18
申请人： Pin-Chin Connie Wang , Paul R. Besser
发明人： Pin-Chin Connie Wang , Paul R. Besser
IPC分类号： H01L2144
CPC分类号： H01L21/76877 , H01L21/2855 , H01L21/76843 , H01L21/76858 , H01L21/76864 , H01L21/76873 , H01L21/76874 , H01L21/76886
摘要： A method of performing a two stage anneal in the formation of an alloy interconnect can include forming a via aperture in a dielectric layer where the via aperture provides an area for formation of a via, providing a seed layer along lateral side walls of the via aperture, rapid thermal annealing the seed layer to facilitate copper grain growth in the via, and slowly annealing the seed layer to facilitate desired distribution of alloy doping. The use of two anneals-one fast (e.g., 60 seconds) at lower temperatures (e.g., 150° C. to 250° C.) and one slow (e.g., minutes to several hours) at higher temperatures (e.g., 200° C. to 450° C.)—helps to control grain growth and alloy doping distribution.
摘要翻译：在合成互连的形成中执行两阶段退火的方法可以包括在电介质层中形成通孔，其中通孔孔提供用于形成通孔的区域，沿通孔孔的横向侧壁提供种子层，快速热退火种子层以促进通孔中的铜晶粒生长，并缓慢退火籽晶层以促进合金掺杂的期望分布。在较高温度（例如，200℃）下，使用两个退火 - 一个快速（例如，60秒）在较低的温度（例如，150℃至250℃）和一个缓慢（例如，几分钟至数小时）至450℃） - 有助于控制晶粒生长和合金掺杂分布。

19. 发明授权

US06555909B1 Seedless barrier layers in integrated circuits and a method of manufacture therefor 有权
标题翻译：集成电路中的无核屏障层及其制造方法
公开(公告)号：US06555909B1
公开(公告)日：2003-04-29
申请号：US09760422
申请日：2001-01-11
申请人： Sergey D. Lopatin , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Pin-Chin Connie Wang
IPC分类号： H01L2352
CPC分类号： H01L23/53238 , H01L23/53223 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. A seedless barrier layer lines the opening, and a conductor core fills the opening over the seedless barrier layer. The barrier layer is deposited in the opening and contains atomic layers of barrier material which bonds to the dielectric layer, an intermediate material which bonds to the barrier material layer and to the conductor core, and a conductor core material which bonds to the intermediate material. The conductor core bonds to the conductor core material.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。在半导体衬底上形成器件电介质层，器件电介质层上的沟道电介质层上形成有开口。阻挡层对通道开口进行排列，并且导体芯填充阻挡层上的开口。无核屏障层对开口进行排列，并且导体芯填充无核阻挡层上的开口。阻挡层沉积在开口中并且包含键合到电介质层的阻挡材料的原子层，结合到阻挡材料层和导体芯的中间材料以及与中间材料结合的导体芯材料。导体芯与导体芯材料结合。

20. 发明授权

US06541860B1 Barrier-to-seed layer alloying in integrated circuit interconnects 失效
标题翻译：集成电路互连中的屏蔽到种子层合金化
公开(公告)号：US06541860B1
公开(公告)日：2003-04-01
申请号：US09875457
申请日：2001-06-05
申请人： Christy Mei-Chu Woo , Pin-Chin Connie Wang , Joffre F. Bernard
发明人： Christy Mei-Chu Woo , Pin-Chin Connie Wang , Joffre F. Bernard
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/76855 , H01L21/76858 , H01L21/76873 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and a method for manufacture thereof are provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. An opening is formed in the dielectric layer. A barrier layer with an alloying element is deposited to line the opening in the dielectric layer. A conductor core is deposited on the barrier layer to fill the opening and connect to the semiconductor device. The conductor core is annealed causing migration of the alloy element into the conductor core.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。在半导体衬底上形成器件电介质层。在电介质层中形成开口。沉积具有合金元素的阻挡层以使介电层中的开口线对齐。导体芯沉积在阻挡层上以填充开口并连接到半导体器件。导体芯退火，导致合金元件迁移到导体芯中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式