专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20150241949A1 MECHANISM TO PROVIDE WORKLOAD AND CONFIGURATION-AWARE DETERMINISTIC PERFORMANCE FOR MICROPROCESSORS 有权
标题翻译：为微处理器提供工作负载和配置 - 确定性能的机制
公开(公告)号：US20150241949A1
公开(公告)日：2015-08-27
申请号：US14697541
申请日：2015-04-27
申请人： Ankush Varma , Krishnakanth V. Sistla , Martin T. Rowland , Chris Poirier , Eric J. Dehaemer , Avinash N. Ananthakrishnan , Jeremy J. Shrall , Xiuting C. Man , Stephen H. Gunther , Krishna K. Rangan , Devadatta V. Bodas , Don Soltis , Hang T. Nguyen , Cyprian W. Woo , Thi Dang
发明人： Ankush Varma , Krishnakanth V. Sistla , Martin T. Rowland , Chris Poirier , Eric J. Dehaemer , Avinash N. Ananthakrishnan , Jeremy J. Shrall , Xiuting C. Man , Stephen H. Gunther , Krishna K. Rangan , Devadatta V. Bodas , Don Soltis , Hang T. Nguyen , Cyprian W. Woo , Thi Dang
IPC分类号： G06F1/32 , G06F1/20
CPC分类号： G06F1/3243 , G06F1/206 , G06F1/28 , G06F1/3206 , Y02D10/152
摘要： One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.
摘要翻译：装置的一个实施例包括具有处理器和裸片上非易失性存储资源的半导体芯片。片上非易失性存储器可以为处理器的相同性能状态的不同配置和处理器的使用情况存储不同的适当的性能相关信息。

12. 发明申请

US20140173297A1 Performing Frequency Coordination In A Multiprocessor System 有权
标题翻译：在多处理器系统中执行频率协调
公开(公告)号：US20140173297A1
公开(公告)日：2014-06-19
申请号：US13716712
申请日：2012-12-17
申请人： Ankush Varma , Krishnakanth V. Sistla , Ian M. Steiner , Vivek Garg , Chris Poirier , Martin T. Rowland
发明人： Ankush Varma , Krishnakanth V. Sistla , Ian M. Steiner , Vivek Garg , Chris Poirier , Martin T. Rowland
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/32 , G06F1/3203 , G06F1/329 , G06F9/5044 , G06F9/505 , G06F13/00 , G06F15/17325 , G06T1/20 , Y02D10/126
摘要： In an embodiment, a processor includes a core to execute instructions, uncore logic coupled to the core, and a power controller to control a power consumption level. The power controller is configured to determine an activity level of the processor and responsive to this level, to generate a request for communication to a second processor coupled to the processor to request frequency coordination between the processors. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括执行指令的核心，耦合到核心的非逻辑逻辑以及用于控制功耗水平的功率控制器。功率控制器被配置为确定处理器的活动级别并响应于该级别，以产生与耦合到处理器的第二处理器通信以请求处理器之间的频率协调的请求。描述和要求保护其他实施例。

13. 发明申请

US20140129858A1 METHOD AND APPARATUS FOR SETTING AN I/O BANDWIDTH-BASED PROCESSOR FREQUENCY FLOOR 有权
标题翻译：用于设置基于I / O带宽处理器频率地板的方法和装置
公开(公告)号：US20140129858A1
公开(公告)日：2014-05-08
申请号：US13992706
申请日：2011-12-21
申请人： Ankush Varma , Ian M. Steiner , Krishnakanth V. Sistla , Matthew M. Bace , Vivek Garg , Martin T. Rowland , Jeffrey S. Wilder
发明人： Ankush Varma , Ian M. Steiner , Krishnakanth V. Sistla , Matthew M. Bace , Vivek Garg , Martin T. Rowland , Jeffrey S. Wilder
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F13/382
摘要： An apparatus and method for managing a frequency of a computer processor. The apparatus includes a power control unit (PCU) to manage power in a computer processor. ThePCU includes a data collection module to obtain transaction rate data from a plurality of communication ports in the computer processor and a frequency control logic module coupled to the data collection module, the frequency control logic to calculate a minimum processor interconnect frequency for the plurality of communication ports to handle traffic without significant added latency and to override the processor interconnect frequency to meet the calculated minimum processor interconnect frequency.
摘要翻译：一种用于管理计算机处理器的频率的装置和方法。该装置包括用于管理计算机处理器中的电力的功率控制单元（PCU）。 PCU包括数据采集模块，用于从计算机处理器中的多个通信端口获得交易速率数据，以及耦合到数据收集模块的频率控制逻辑模块，频率控制逻辑来计算多个通信端口来处理流量而没有显着增加的延迟，并且覆盖处理器互连频率以满足计算的最小处理器互连频率。

14. 发明申请

US20130332753A1 DYNAMIC POWER LIMIT SHARING IN A PLATFORM 有权
标题翻译：动态功率限制在平台中共享
公开(公告)号：US20130332753A1
公开(公告)日：2013-12-12
申请号：US13976687
申请日：2012-03-29
申请人： Ankush Varma , Krishnakanth V. Sistla , Cesar A. Quiroz , Vivek Garg , Martin T. Rowland , Inder M. Sodhi , James S. Burns
发明人： Ankush Varma , Krishnakanth V. Sistla , Cesar A. Quiroz , Vivek Garg , Martin T. Rowland , Inder M. Sodhi , James S. Burns
IPC分类号： G06F1/26
CPC分类号： G06F1/3287 , G06F1/26 , G06F1/324 , G06F1/3275 , G06F1/3296 , Y02D10/126 , Y02D10/14 , Y02D10/172
摘要： A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.
摘要翻译：一种用于在平台中的模块之间动态功率限制共享的方法和装置。在本发明的一个实施例中，平台包括处理器和存储器模块。通过扩展功率域以包括处理器和存储器模块，能够在处理器和存储器模块之间动态共享平台的功率预算。对于低带宽工作负载，功率预算的动态共享为处理器通过使用存储器电源中的余量增加频率提供了重要机会，反之亦然。这在本发明的一个实施例中能够实现相同的总平台功率预算的更高峰值性能。

15. 发明申请

US20140195828A1 DYNAMICALLY MEASURING POWER CONSUMPTION IN A PROCESSOR 有权
标题翻译：在处理器中动态测量功耗
公开(公告)号：US20140195828A1
公开(公告)日：2014-07-10
申请号：US13996266
申请日：2012-03-30
申请人： Ankush Varma , Krishnakanth V. Sistla , Martin T. Rowland , Vivek Garg , James S. Burns
发明人： Ankush Varma , Krishnakanth V. Sistla , Martin T. Rowland , Vivek Garg , James S. Burns
IPC分类号： G01R21/133 , G06F1/32
CPC分类号： G01R21/133 , G06F1/26 , G06F1/3203 , G06F1/3206 , G06F1/324 , G06F1/3243 , G06F1/3296 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： In one embodiment, the present invention includes a processor having multiple cores to independently execute instructions, a first sensor to measure a first power consumption level of the processor based at least in part on events occurring on the cores, and a hybrid logic to combine the first power consumption level and a second power consumption level. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有多个核以独立执行指令的处理器，第一传感器至少部分地基于在核上发生的事件来测量处理器的第一功率消耗水平，以及混合逻辑，第一功率消耗水平和第二功耗水平。描述和要求保护其他实施例。

16. 发明申请

US20140181538A1 Controlling Configurable Peak Performance Limits Of A Processor 有权
标题翻译：控制处理器的可配置峰值性能限制
公开(公告)号：US20140181538A1
公开(公告)日：2014-06-26
申请号：US13724732
申请日：2012-12-21
申请人： Jeremy J. Shrall , Stephen H. Gunther , Krishnakanth V. Sistla , Ryan D. Wells , Shaun M. Conrad
发明人： Jeremy J. Shrall , Stephen H. Gunther , Krishnakanth V. Sistla , Ryan D. Wells , Shaun M. Conrad
IPC分类号： G06F1/26
CPC分类号： G06F1/3243 , G06F1/324 , G06F3/14 , Y02D10/152
摘要： In one embodiment, the present invention includes a processor having a plurality of cores each to execute instructions, a non-volatile storage to store maximum peak operating frequency values each a function of a given number of active cores, a configuration storage to store frequency limits each corresponding to one of the maximum peak operating frequency values or a configurable clip frequency value less than the maximum peak operating frequency value. In turn, a power controller is configured to limit operating frequency of the cores to a corresponding frequency limit obtained from the configuration storage. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有多个核的处理器，每个核每个用于执行指令;非易失性存储器，用于存储最大峰值操作频率值，每一个是给定数量的活动核心的功能;存储频率限制的配置存储每个对应于最大峰值工作频率值之一或可配置的剪辑频率值小于最大峰值工作频率值。反过来，功率控制器被配置为将芯的操作频率限制到从配置存储获得的相应频率限制。描述和要求保护其他实施例。

17. 发明申请

US20140006673A1 UTILIZATION-AWARE LOW-OVERHEAD LINK-WIDTH MODULATION FOR POWER REDUCTION IN INTERCONNECTS 有权
标题翻译：用于互连中功率降低的应用 - 低电平连接宽度调节
公开(公告)号：US20140006673A1
公开(公告)日：2014-01-02
申请号：US13536852
申请日：2012-06-28
申请人： Ankush Varma , Buck W. Gremel , Robert G. Blankenship , Krishnakanth V. Sistla , Michael F. Cole
发明人： Ankush Varma , Buck W. Gremel , Robert G. Blankenship , Krishnakanth V. Sistla , Michael F. Cole
IPC分类号： G06F13/40
CPC分类号： G06F13/4027 , G06F1/3203 , G06F1/3253 , G06F13/4018 , G06F13/4221 , G06F15/16 , Y02D10/151
摘要： Methods and apparatus relating to low-overhead utilization-aware link-width modulation to reduce power consumption in interconnects are described. In one embodiment, a link width modulation logic adjusts the width of an interconnect link. More particularly, the link width modulation logic causes the interconnect link to transition from a first width to a second width based on comparison of a utilization value associated with the interconnect link against at least one of a plurality of utilization threshold values. Other embodiments are also disclosed and claimed.
摘要翻译：描述了与低开销利用感知链路宽度调制相关的方法和装置，以减少互连中的功耗。在一个实施例中，链路宽度调制逻辑调整互连链路的宽度。更具体地，链路宽度调制逻辑使得互连链路基于与互连链路相关联的利用值与多个利用阈值中的至少一个的比较从第一宽度转换到第二宽度。还公开并要求保护其他实施例。

18. 发明授权

US08407432B2 Cache coherency sequencing implementation and adaptive LLC access priority control for CMP 失效
标题翻译：缓存一致性排序实现和CMP自适应LLC访问优先级控制
公开(公告)号：US08407432B2
公开(公告)日：2013-03-26
申请号：US11173917
申请日：2005-06-30
申请人： Zhong-Ning Cai , Krishnakanth V. Sistla , Yen-Cheng Liu , Jeffrey D. Gilbert
发明人： Zhong-Ning Cai , Krishnakanth V. Sistla , Yen-Cheng Liu , Jeffrey D. Gilbert
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0817 , G06F2212/507
摘要： A method and apparatus for cache coherency sequencing implementation and an adaptive LLC access priority control is disclosed. One embodiment provides mechanisms to resolve last level cache access priority among multiple internal CMP cores, internal snoops and external snoops. Another embodiment provides mechanisms for implementing cache coherency in multi-core CMP system.
摘要翻译：公开了一种用于高速缓存一致性排序实现和自适应LLC访问优先级控制的方法和装置。一个实施例提供了解决多个内部CMP核心，内部窥探和外部窥探之间的最后一级高速缓存访问优先级的机制。另一实施例提供了用于在多核CMP系统中实现高速缓存一致性的机制。

19. 发明授权

US07590805B2 Monitor implementation in a multicore processor with inclusive LLC 有权
标题翻译：在包含有限责任公司的多核处理器中监视实现
公开(公告)号：US07590805B2
公开(公告)日：2009-09-15
申请号：US11323368
申请日：2005-12-29
申请人： Krishnakanth V. Sistla , Bryan L. Spry
发明人： Krishnakanth V. Sistla , Bryan L. Spry
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F12/0822 , G06F12/0831 , G06F2212/306
摘要： A method and apparatus to implement monitor primitives when a processor employs an inclusive shared last level cache. By the employing an inclusive last level cache, the processor is almost always able to complete a monitor transaction without requiring self snooping through the system interconnect.
摘要翻译：当处理器采用包含共享的最后一级高速缓存时，实现监视器原语的方法和装置。通过采用包容性最后一级缓存，处理器几乎总是能够完成监视器事务，而不需要通过系统互连自窥。

20. 发明授权

US07502889B2 Home node aware replacement policy for caches in a multiprocessor system 有权
标题翻译：多处理器系统中缓存的家庭节点感知替换策略
公开(公告)号：US07502889B2
公开(公告)日：2009-03-10
申请号：US11320627
申请日：2005-12-30
申请人： Krishnakanth V. Sistla
发明人： Krishnakanth V. Sistla
IPC分类号： G06F12/12
CPC分类号： G06F12/121 , G06F12/0813 , G06F2212/2542
摘要： A home node aware replacement policy for a cache chooses to evict lines which belong to local memory over lines which belong to remote memory, reducing the average transaction cost of incorrect cache line replacements. With each entry, the cache stores a t-bit cost metric (t≧1) representing a relative distance between said cache and an originating memory for the respective cache entry. Responsive to determining that no cache entry corresponds to an access request, the replacement policy selects a cache entry for eviction from the cache based at least in part on the t-bit cost metric. The selected cache entry is then evicted from the cache.
摘要翻译：缓存的家庭节点感知替换策略选择通过属于远程存储器的线路驱逐属于本地存储器的线路，从而降低不正确的高速缓存行替换的平均交易成本。对于每个条目，高速缓存存储表示相应高速缓存条目的所述高速缓存和起始存储器之间的相对距离的t位成本度量（t> = 1）。响应于确定没有高速缓存条目对应于访问请求，替换策略至少部分地基于t位成本度量从高速缓存选择用于逐出的高速缓存条目。然后，所选缓存条目从缓存中逐出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式