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11. 发明授权

US07888166B2 Method to form high efficiency GST cell using a double heater cut 有权
标题翻译：使用双加热器切割形成高效GST电池的方法
公开(公告)号：US07888166B2
公开(公告)日：2011-02-15
申请号：US12724266
申请日：2010-03-15
申请人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
发明人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
IPC分类号： H01L21/00 , H01L29/18
CPC分类号： H01L27/2463 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described.
摘要翻译：本发明的实施例提供一种方法，其包括提供包括多个单元的晶片，每个单元包括至少一个发射极。所述方法还包括在晶片的字线方向上执行平版印刷操作，以形成预热器元件布置，在跨过预热器元件布置的晶片的位线方向上执行平版印刷操作，以形成预加工元件 - 加热器元件，并且跨越预热器元件的一部分在字线方向上执行光刻操作，以形成邻近每个发射器的加热元件。还描述了其它实施例。

12. 发明授权

US07745809B1 Ultra high density phase change memory having improved emitter contacts, improved GST cell reliability and highly matched UHD GST cells using column mirco-trench strips 有权
标题翻译：具有改进的发射体触点，改善的GST电池可靠性的超高密度相变存储器以及使用柱式微通道条带的高度匹配的UHD GST电池
公开(公告)号：US07745809B1
公开(公告)日：2010-06-29
申请号：US12062444
申请日：2008-04-03
申请人： Pantas Sutardja , Albert Wu , Chien-Chuan Wei , Runzi Chang , Winston Lee , Peter Lee
发明人： Pantas Sutardja , Albert Wu , Chien-Chuan Wei , Runzi Chang , Winston Lee , Peter Lee
IPC分类号： H01L29/04
CPC分类号： H01L45/1233 , H01L27/0688 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/126 , H01L45/1293 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： Embodiments of the present invention provide an apparatus comprising a substrate comprising an emitter layer and at least one emitter interface adjacent to the emitter layer, and a metal protective layer on a top surface of the at least one emitter interface. A method of manufacturing such an apparatus is also disclosed. The method may include performing plasma nitridation directed at column micro-trench strips. Other embodiments are also described.
摘要翻译：本发明的实施例提供了一种装置，其包括：衬底，其包括发射极层和与发射极层相邻的至少一个发射极接口，以及在所述至少一个发射极接口的顶表面上的金属保护层。还公开了制造这种装置的方法。该方法可以包括执行针对柱状微沟槽条带的等离子体氮化。还描述了其它实施例。

13. 发明申请

US20080246015A1 METHOD TO FORM HIGH EFFICIENCY GST CELL USING A DOUBLE HEATER CUT 有权
标题翻译：使用双重加热器切割形成高效GST细胞的方法
公开(公告)号：US20080246015A1
公开(公告)日：2008-10-09
申请号：US12060792
申请日：2008-04-01
申请人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
发明人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
IPC分类号： H01L45/00
CPC分类号： H01L27/2463 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described.
摘要翻译：本发明的实施例提供一种方法，其包括提供包括多个单元的晶片，每个单元包括至少一个发射极。所述方法还包括在晶片的字线方向上执行平版印刷操作，以形成预热器元件布置，在跨过预热器元件布置的晶片的位线方向上执行平版印刷操作，以形成预加工元件 - 加热器元件，并且跨越预热器元件的一部分在字线方向上执行光刻操作，以形成邻近每个发射器的加热元件。还描述了其它实施例。

14. 发明授权

US07994052B1 High-density patterning 有权
标题翻译：高密度图案化
公开(公告)号：US07994052B1
公开(公告)日：2011-08-09
申请号：US12045528
申请日：2008-03-10
申请人： Pantas Sutardja , Albert Wu , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
发明人： Pantas Sutardja , Albert Wu , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
IPC分类号： H01L21/44
CPC分类号： H01L21/76816
摘要： Methods for patterning high-density features are described herein. Embodiments of the present invention provide a method comprising patterning a first subset of a pattern, the first subset configured to form a plurality of lines over the substrate, and patterning a second subset of the pattern, the second subset configured to form a plurality of islands over the substrate, wherein said patterning the first subset and said patterning the second subset comprise at least two separate patterning operations.
摘要翻译：本文描述了用于图案化高密度特征的方法。本发明的实施例提供了一种方法，包括对图案的第一子集进行图案化，所述第一子集被配置成在所述衬底上形成多个线，以及图案化所述图案的第二子集，所述第二子集被配置为形成多个岛其中所述图案化所述第一子集并且所述图案化所述第二子集包括至少两个单独的图案化操作。

15. 发明授权

US07985616B1 Methods to form wide heater trenches and to form memory cells to engage heaters 有权
标题翻译：形成宽加热器沟槽并形成记忆单元以接合加热器的方法
公开(公告)号：US07985616B1
公开(公告)日：2011-07-26
申请号：US12060810
申请日：2008-04-01
申请人： Pantas Sutardja , Albert Wu , Chien-Chuan Wei , Runzi Chang , Winston Lee , Peter Lee
发明人： Pantas Sutardja , Albert Wu , Chien-Chuan Wei , Runzi Chang , Winston Lee , Peter Lee
IPC分类号： H01L21/00
CPC分类号： H01L27/2463 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1675
摘要： Embodiments of the present invention provide a method that includes providing a wafer including multiple cells, each cell including at least one emitter, and performing a lithographic operation on the wafer. The lithographic operation comprises forming heater trenches adjacent the emitters, each heater trench having a width that extends over at least respective portions of two cells. Other embodiments are also described.
摘要翻译：本发明的实施例提供一种方法，其包括提供包括多个单元的晶片，每个单元包括至少一个发射极，并在晶片上执行光刻操作。光刻操作包括在发射器附近形成加热器沟槽，每个加热器沟槽具有在两个单元的至少相应部分上延伸的宽度。还描述了其它实施例。

16. 发明授权

US07807539B1 Ion implantation and process sequence to form smaller base pick-up 有权
标题翻译：离子注入和工艺顺序形成较小的基座
公开(公告)号：US07807539B1
公开(公告)日：2010-10-05
申请号：US12056052
申请日：2008-03-26
申请人： Pantas Sutardja , Albert Wu , Chien-Chuan Wei , Runzi Chang , Winston Lee , Peter Lee
发明人： Pantas Sutardja , Albert Wu , Chien-Chuan Wei , Runzi Chang , Winston Lee , Peter Lee
IPC分类号： H01L21/8222 , H01L21/331
CPC分类号： H01L29/0804 , H01L29/66272
摘要： Methods for forming a bipolar junction transistor device are described herein. A method for forming the bipolar junction transistor device may include doping a first portion of a substrate with a first dopant to form a base pick-up region, and after doping the first portion of the substrate, doping a second portion of the substrate with a second dopant to form at least one emitter region. A bipolar junction transistor device may include a floating collector, in which case the bipolar junction transistor device may be operated as a diode for improved emitter current.
摘要翻译：本文描述了用于形成双极结型晶体管器件的方法。用于形成双极结型晶体管器件的方法可以包括用第一掺杂剂掺杂衬底的第一部分以形成基极拾取区域，并且在掺杂衬底的第一部分之后，将衬底的第二部分用第二掺杂剂以形成至少一个发射极区域。双极结型晶体管器件可以包括浮动集电极，在这种情况下，双极结型晶体管器件可以作为二极管来工作，以改善发射极电流。

17. 发明授权

US07704805B1 Fuse structures, methods of making and using the same, and integrated circuits including the same 有权
标题翻译：保险丝结构，制造和使用它们的方法以及包括其的集成电路
公开(公告)号：US07704805B1
公开(公告)日：2010-04-27
申请号：US12012723
申请日：2008-02-04
申请人： Chuan-Cheng Cheng , Shuhua Yu , Roawen Chen , Albert Wu
发明人： Chuan-Cheng Cheng , Shuhua Yu , Roawen Chen , Albert Wu
IPC分类号： H01L21/82 , H01L21/8238 , H01L21/336
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).
摘要翻译：保险丝结构，包括该结构的集成电路，以及使用该保险丝的结构和（重新）配置电路的方法。熔丝结构通常包括（a）具有至少两个电耦合到其上的电路元件的导电结构，（b）导电结构上的电介质层，和（c）第一介电层和导电结构上的第一透镜，以至少部分地将光聚焦到导电结构上。制造该结构的方法通常包括以下步骤：（1）形成电耦合到第一和第二电路元件的导电结构，（2）在其上形成介电层，和（3）在电介质层上或之上形成透镜，在导电结构之上，透镜被配置为至少部分地将光聚焦到导电结构上。（重新）配置电路的方法通常包括以下步骤：（i）在电路表面上或附近照射足够的电气断开位于透镜下方的对应的第一保险丝的至少一个透镜，并且禁用电路的第一配置，以及（ii）在该电路表面上或其附近照射至少一个其他透镜，足以使位于该透镜下方的对应的第二保险丝电气断开并使电路能够进行第二配置。该结构和方法有利地提供具有改善的可靠性和更小的芯片面积的熔丝结构，从而提高制造工艺的产量和每个晶片的模具数量（总和良好）。

18. 发明授权

US06940107B1 Fuse structures, methods of making and using the same, and integrated circuits including the same 有权
标题翻译：保险丝结构，制造和使用它们的方法以及包括其的集成电路
公开(公告)号：US06940107B1
公开(公告)日：2005-09-06
申请号：US10734779
申请日：2003-12-12
申请人： Chuan-Cheng Cheng , Shuhua Yu , Roawen Chen , Albert Wu
发明人： Chuan-Cheng Cheng , Shuhua Yu , Roawen Chen , Albert Wu
IPC分类号： H01L23/525 , H01L27/10
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).
摘要翻译：保险丝结构，包括该结构的集成电路，以及使用该保险丝的结构和（重新）配置电路的方法。熔丝结构通常包括（a）具有至少两个电耦合到其上的电路元件的导电结构，（b）导电结构上的电介质层，和（c）第一介电层和导电结构上的第一透镜，以至少部分地将光聚焦到导电结构上。制造该结构的方法通常包括以下步骤：（1）形成电耦合到第一和第二电路元件的导电结构，（2）在其上形成介电层，和（3）在电介质层上或之上形成透镜，在导电结构之上，透镜被配置为至少部分地将光聚焦到导电结构上。（重新）配置电路的方法通常包括以下步骤：（i）在电路表面上或附近照射足够的电气断开位于透镜下方的对应的第一保险丝的至少一个透镜，并且禁用电路的第一配置，以及（ii）在该电路表面上或其附近照射至少一个其他透镜，足以使位于该透镜下方的对应的第二保险丝电气断开并使电路能够进行第二配置。该结构和方法有利地提供具有改善的可靠性和更小的芯片面积的熔丝结构，从而提高制造工艺的产量和每个晶片的模具数量（总和良好）。

19. 发明授权

US08609528B1 High-density patterning 失效
标题翻译：高密度图案化
公开(公告)号：US08609528B1
公开(公告)日：2013-12-17
申请号：US13204370
申请日：2011-08-05
申请人： Pantas Sutardja , Albert Wu , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
发明人： Pantas Sutardja , Albert Wu , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816
摘要： Methods for patterning high-density features are described herein. Embodiments of the present invention provide a method comprising patterning a first subset of a pattern, the first subset configured to form a plurality of lines over the substrate, and patterning a second subset of the pattern, the second subset configured to form a plurality of islands over the substrate, wherein said patterning the first subset and said patterning the second subset comprise at least two separate patterning operations.
摘要翻译：本文描述了用于图案化高密度特征的方法。本发明的实施例提供了一种方法，包括对图案的第一子集进行图案化，所述第一子集被配置成在所述衬底上形成多个线，以及图案化所述图案的第二子集，所述第二子集被配置为形成多个岛其中所述图案化所述第一子集并且所述图案化所述第二子集包括至少两个单独的图案化操作。

20. 发明授权

US07863709B1 Low base resistance bipolar junction transistor array 有权
标题翻译：低基极电阻双极结晶体管阵列
公开(公告)号：US07863709B1
公开(公告)日：2011-01-04
申请号：US12104254
申请日：2008-04-16
申请人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
发明人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
IPC分类号： H01L27/082
CPC分类号： H01L27/1026
摘要： Methods and apparatuses directed to low base resistance bipolar junction transistor (BJT) devices are described herein. A low base resistance BJT device may include a collector layer, a base layer formed on the collector layer, a plurality of isolation trench lines formed in the base layer and extending into the collector layer, and a plurality of polysilicon lines formed on the base layer parallel to and overlapping the plurality of isolation trench lines. The base layer may be N-doped or P-doped.
摘要翻译：本文描述了针对低基极电阻双极结型晶体管（BJT）器件的方法和装置。低电阻BJT器件可以包括集电极层，形成在集电极层上的基极层，形成在基极层中并延伸到集电极层中的多个隔离沟槽线，以及形成在基极层上的多个多晶硅线平行于并重叠多个隔离沟槽线。基层可以是N掺杂或P掺杂的。

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