专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US6115728A Fast fourier transforming apparatus and method, variable bit reverse circuit, inverse fast fourier transforming apparatus and method, and OFDM receiver and transmitter 失效
标题翻译：快速傅里叶变换装置和方法，可变位反向电路，反向快速傅里叶变换装置和方法，以及OFDM接收机和发射机
公开(公告)号：US6115728A
公开(公告)日：2000-09-05
申请号：US010499
申请日：1998-01-21
申请人： Yuji Nakai , Akihiro Furuta
发明人： Yuji Nakai , Akihiro Furuta
IPC分类号： G06F17/14 , G06F15/00
CPC分类号： G06F17/141
摘要： In fast Fourier transform, a necessary memory capacity is decreased, thereby decreasing a cost. The fast Fourier transform is performed on a symbol stored in a random access memory (RAM) by a butterfly operation unit in accordance with a RAM address generated by a RAM address generator. A RAM address conversion unit converts an input/output dummy address into an input/output real address by conducting bit reverse by a frequency specified in accordance with an input/output bit reverse signal, and converts a butterfly operation dummy address into a butterfly operation real address by conducting the bit reverse by a frequency specified in accordance with a butterfly operation bit reverse signal. In this manner, among output data of one symbol and input data of another symbol to be stored in the RAM subsequently to the output data of the one symbol, data having a common index indicating their orders in the symbols can be stored at the same address in the RAM. As a result, symbol input and symbol output can be overlapped.
摘要翻译：在快速傅里叶变换中，必要的存储容量减少，从而降低成本。根据由RAM地址发生器产生的RAM地址，通过蝶形运算单元对存储在随机存取存储器（RAM）中的符号进行快速傅立叶变换。 RAM地址转换单元通过根据输入/输出位反向信号指定的频率进行位反转而将输入/输出虚拟地址转换为输入/输出实地址，并将蝶形运算虚拟地址转换为蝶形运算实际通过根据蝶形运算位反向信号指定的频率进行位反转。以这种方式，在随后的一个符号的输出数据之后的一个符号的输出数据和要存储在RAM中的另一个符号的输入数据之间，具有指示它们在符号中的顺序的公共索引的数据可以存储在相同的地址在RAM中。结果，符号输入和符号输出可以重叠。

12. 发明授权

US07720113B2 Receiving apparatus, receiving system using same, and receiving method thereof 有权
标题翻译：接收装置，使用其的接收系统及其接收方法
公开(公告)号：US07720113B2
公开(公告)日：2010-05-18
申请号：US11547282
申请日：2004-11-18
申请人： Shunsuke Sakai , Yuji Nakai
发明人： Shunsuke Sakai , Yuji Nakai
IPC分类号： H04J3/02
CPC分类号： H04N5/4401 , H04N5/46 , H04N21/4305 , H04N21/4382 , H04N21/4622
摘要： A receiving apparatus (100) includes demodulation parts (101, 102) for receiving the respective one of received signals of broadast systems to output demodulated data and timing clocks synchronized with the respective demodulated data, a clock generating part (103) for outputting, to an A/V decoder (107), the two timing clocks from the demodulation parts (101, 102) as high-rate and low-rate timing clocks and for outputting a control signal for multiplexing the two demodulated data from the demodulation parts (101, 102), and a multiplexing part (104) for multiplexing, based on the control signal, the two demodulated data to output the multiplexed data to the A/V decoder (107). The A/V decoder (107) receives the multiplexed data and timing clocks from the receiving apparatus (100) to process the video/audio signals of each broadcast.
摘要翻译：一种接收装置（100），包括用于接收广播系统的接收信号中的相应一个的解调部分（101,102），以输出与各个解调数据同步的解调数据和定时时钟;时钟发生部分（103），用于输出 A / V解码器（107），来自解调部分（101,102）的两个定时时钟作为高速和低速定时时钟，并且用于输出用于从解调部分（101）复用两个解调数据的控制信号，102）和多路复用部分（104），用于基于控制信号多路复用两个解调数据，以将复用的数据输出到A / V解码器（107）。 A / V解码器（107）从接收装置（100）接收多路复用数据和定时时钟，以处理每个广播的视频/音频信号。

13. 发明授权

US06887111B2 Electrical/photoelectric conversion dual connector 失效
标题翻译：电/光电转换双连接器
公开(公告)号：US06887111B2
公开(公告)日：2005-05-03
申请号：US10325992
申请日：2002-12-19
申请人： Yuji Nakai , Yasuro Ishimori
发明人： Yuji Nakai , Yasuro Ishimori
IPC分类号： G02B6/36 , G02B6/38 , G02B6/42 , H01R12/36 , H01R13/46 , H01R13/514 , H01R13/66 , H01R24/00 , H01R17/00
CPC分类号： G02B6/4292 , G02B6/3817 , G02B6/4255 , G02B6/4261 , G02B6/4293 , H01R12/725
摘要： A dual connector including a first unit serving as the electrical connector element, and a second unit serving as the photoelectric conversion connector element which is attachable to and detachable from a rear end portion of the first unit. A first soldering terminal of the surface mount type disposed on the first unit is placed on a side portion of the body, and a second soldering terminal of the surface mount type disposed on the second unit is placed on a rear portion of a holder.
摘要翻译：一种双连接器，包括用作电连接器元件的第一单元和用作光电转换连接器元件的第二单元，其可附接到第一单元的后端部分并且可从其拆卸。设置在第一单元上的表面安装型的第一焊接端子放置在主体的侧部，并且设置在第二单元上的表面安装型的第二焊接端子放置在保持器的后部。

14. 发明授权

US06728926B1 Encoding rate detection method and encoding rate detection device 失效
标题翻译：编码率检测方法和编码速率检测装置
公开(公告)号：US06728926B1
公开(公告)日：2004-04-27
申请号：US09831636
申请日：2001-05-11
申请人： Takashi Kakemizu , Takehiro Kamada , Yuji Nakai
发明人： Takashi Kakemizu , Takehiro Kamada , Yuji Nakai
IPC分类号： H03M1300
CPC分类号： H03M13/33 , H03M13/01 , H04L1/0046 , H04L7/041
摘要： In accordance with a rate detecting method for detecting a predetermined rate at which a received signal has been coded, the coded signal is decoded based on a first synchronizing signal having a frequency corresponding to a first rate such that a first decoded signal (ST11) is generated and then it is judged whether or not synchronization is determined for the first decoded signal (ST12). If the synchronization cannot be determined, there is generated only a second synchronizing signal having a frequency corresponding to a second rate having a difference between itself and a first rate which is smaller than a permissible value of the rate determined by the lower and upper values of the rate (ST13, ST17).
摘要翻译：根据用于检测接收信号已被编码的预定速率的速率检测方法，基于具有与第一速率对应的频率的第一同步信号来解码编码信号，使得第一解码信号（ST11）为然后判断是否确定了第一解码信号的同步（ST12）。如果不能确定同步，则只产生第二同步信号，该第二同步信号具有对应于第二速率的频率，该第二速率具有自身与第一速率之间的差值，该第一速率小于由下限和下限值确定的速率的允许值率（ST13，ST17）。

15. 发明授权

US07057968B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07057968B2
公开(公告)日：2006-06-06
申请号：US11075739
申请日：2005-03-10
申请人： Naoki Kuroda , Yuji Nakai
发明人： Naoki Kuroda , Yuji Nakai
IPC分类号： G11C8/00
CPC分类号： G11C11/413 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C11/412 , G11C2207/107
摘要： Logic circuits access a memory block by way of an access circuit. The memory block, which is formed of a mixed configuration of DRAMs and an SRAM, realizes the desired memory space. A data output register is provided at the output side of the SRAM so as to synchronize data output timing from the DRAMs with data output timing from the SRAM.
摘要翻译：逻辑电路通过访问电路访问存储块。由DRAM和SRAM的混合配置形成的存储器块实现期望的存储器空间。在SRAM的输出侧提供数据输出寄存器，以使来自DRAM的数据输出定时与来自SRAM的数据输出定时同步。

16. 发明授权

US06990043B2 Semiconductor integrated circuit device having a common DRAM block accessed by a plurality of logic circuits 有权
标题翻译：具有由多个逻辑电路访问的公共DRAM块的半导体集成电路器件
公开(公告)号：US06990043B2
公开(公告)日：2006-01-24
申请号：US11074897
申请日：2005-03-09
申请人： Naoki Kuroda , Yuji Nakai
发明人： Naoki Kuroda , Yuji Nakai
IPC分类号： G11C8/18
CPC分类号： G11C7/10 , G11C7/1006 , G11C2207/107
摘要： A plurality of logic circuits access a DRAM block by way of an access circuit. The operation clock for the DRAM block is set at a higher frequency than the system clock for the logic circuits. Outputs of a first bit width from the logic circuits are subjected to serial/parallel conversion into data of a second bit width and the data is written into the DRAM block.
摘要翻译：多个逻辑电路通过访问电路访问DRAM块。 DRAM块的操作时钟设置在比逻辑电路的系统时钟更高的频率上。来自逻辑电路的第一位宽的输出经过串行/并行转换为第二位宽的数据，并将数据写入DRAM块。

17. 发明申请

US20050207266A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20050207266A1
公开(公告)日：2005-09-22
申请号：US11075739
申请日：2005-03-10
申请人： Naoki Kuroda , Yuji Nakai
发明人： Naoki Kuroda , Yuji Nakai
IPC分类号： G11C11/413 , G11C7/10 , G11C8/00 , G11C11/401 , G11C11/407 , G11C11/412
CPC分类号： G11C11/413 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C11/412 , G11C2207/107
摘要： Logic circuits access a memory block by way of an access circuit. The memory block, which is formed of a mixed configuration of DRAMs and an SRAM, realizes the desired memory space. A data output register is provided at the output side of the SRAM so as to synchronize data output timing from the DRAMs with data output timing from the SRAM.
摘要翻译：逻辑电路通过访问电路访问存储块。由DRAM和SRAM的混合配置形成的存储器块实现期望的存储器空间。在SRAM的输出侧提供数据输出寄存器，以使来自DRAM的数据输出定时与来自SRAM的数据输出定时同步。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式