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11. 发明授权

US08693591B1 Apparatus and method for tuning the frequency of a bandpass filter to an offset frequency around a carrier frequency 失效
标题翻译：用于将带通滤波器的频率调谐到载波频率周围的偏移频率的装置和方法
公开(公告)号：US08693591B1
公开(公告)日：2014-04-08
申请号：US13623406
申请日：2012-09-20
申请人： Phuong Huynh
发明人： Phuong Huynh
IPC分类号： H04L27/06
CPC分类号： H03L7/091 , H03J5/00
摘要： A novel frequency locked loop for tuning a bandpass filter to a small offset frequency around an RF center frequency is provided. The difference between the bandpass filter frequency and the RF center frequency is generated, a frequency locked loop is used to tune the frequency difference to a reference offset frequency.
摘要翻译：提供了一种用于将带通滤波器调谐到围绕RF中心频率的小偏移频率的新型频率锁定环路。产生带通滤波器频率和RF中心频率之间的差异，使用频率锁定环来将频率差调谐到参考偏移频率。

12. 发明申请

US20080025437A1 Quadrature bandpass-sampling delta-sigma communication receiver 审中-公开
标题翻译：正交带通采样Δ-Σ通信接收机
公开(公告)号：US20080025437A1
公开(公告)日：2008-01-31
申请号：US11495683
申请日：2006-07-31
申请人： Phuong Huynh
发明人： Phuong Huynh
IPC分类号： H04L27/00 , H04L27/22
CPC分类号： H04L27/3881 , H03M3/40 , H03M3/424 , H03M3/47
摘要： A quadrature bandpass-sampling analog-to-digital demodulator (QBS-ADD) is provided. A radio frequency (RF) signal is received by a junction summer, which subtracts an in-phase feedback signal and a quadrature feedback signal from the RF signal to produce an error signal. The error signal is then bandpassed and amplified by the RF bandpass filter/amplifier. The amplified signal is bandpass-sampled by two low-resolution analog-to-digital converters clocking in quadrature, and is demodulated and converted into a digital in-phase signal and a digital quadrature signal. The down converted in-phase and quadrature signals are multiplied with two quadrature clocks. The results are converted to two analog signals and fed back to the RF input at the junction summer.
摘要翻译：提供了一个正交带通采样模数和数字解调器（QBS-ADD）。射频（RF）信号通过结点加法器接收，其从RF信号中减去同相反馈信号和正交反馈信号以产生误差信号。然后误差信号被带通并被RF带通滤波器/放大器放大。放大的信号由正交时钟的两个低分辨率模数转换器进行带通采样，并被解调并转换为数字同相信号和数字正交信号。下变频同相和正交信号乘以两个正交时钟。结果转换为两个模拟信号，并在夏季结束时反馈到RF输入。

13. 发明授权

US08816781B2 Apparatus and method to detect frequency difference 有权
标题翻译：检测频率差异的装置和方法
公开(公告)号：US08816781B2
公开(公告)日：2014-08-26
申请号：US13623380
申请日：2012-09-20
申请人： Phuong Huynh
发明人： Phuong Huynh
IPC分类号： H03L7/00 , H03L7/091 , H03L7/089
CPC分类号： H03L7/089 , H03L7/0891 , H03L7/091
摘要： An all-digital frequency detector is provided, which includes a phase-frequency detector receiving a reference clock and an input clock, two sample/hold circuits sampling the phase-frequency detector outputs responsive to a ninety-degree phase shifted reference clock and a ninety-degree phase shifted input clock, a plurality of logical operators to generate an output frequency detection signal and a output clock responsive to the difference between the reference clock and the input clock.
摘要翻译：提供全数字频率检测器，其包括接收参考时钟和输入时钟的相位频率检测器，两个采样/保持电路响应于九十度相移参考时钟和九十分之一个相位频率检测器输出多个相移输入时钟，多个逻辑运算符，以响应于参考时钟和输入时钟之间的差产生输出频率检测信号和输出时钟。

14. 发明申请

US20070063883A1 Pipelined analog to digital converter 审中-公开
标题翻译：流水线模数转换器
公开(公告)号：US20070063883A1
公开(公告)日：2007-03-22
申请号：US11229599
申请日：2005-09-20
申请人： Phuong Huynh , Nitin Sharma
发明人： Phuong Huynh , Nitin Sharma
IPC分类号： H03M1/12
CPC分类号： H03M1/1205 , H03M1/361
摘要： A circuit is provided for receiving an analog signal and providing a digital signal. It includes pre-amplifiers (601, 603, 605, 607), where each pre-amplifier (601, 603, 605, 607) receives an analog signal (Vin) and a respective reference signal (REF1-REFn). Each of the pre-amplifiers (601, 603, 605, 607) produces an output signal responsive to the analog signal and the respective reference signal. For each of the pre-amplifiers (601, 603, 605, 607), there is provided two or more latches (615, 617, 619, 621, 623, 625) corresponding thereto. Each of the latches (615, 617, 619, 621, 623, 625) receives the output signal and a clock signal and produces a respective digital signal responsive thereto, the clock signal being interleaved. For each of the pre-amplifiers (601, 603, 605, 607), there is a multiplexer (627, 629, 631) corresponding thereto. The multiplexer (627, 629, 631) multiplexes between the respective digital signals to produce a bit in a digital signal.
摘要翻译：提供用于接收模拟信号并提供数字信号的电路。它包括预放大器（601,603,605,607），其中每个前置放大器（601,603,605,607）接收模拟信号（Vin）和相应的参考信号（REF 1 -REFn）。每个前置放大器（601,603,605,607）产生响应于模拟信号和相应参考信号的输出信号。对于每个前置放大器（601,603,605,607），提供两个或多个对应于其的锁存器（615,617,619,621,663,625）。每个锁存器（615,617,619,621,623,625）接收输出信号和时钟信号，并响应于此产生相应的数字信号，时钟信号被交织。对于每个前置放大器（601,603,605,607），存在对应于其的多路复用器（627,629,631）。复用器（627,629,631）在相应的数字信号之间复用以产生数字信号中的位。

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