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11. 发明申请

US20120191915A1 EFFICIENT LEVEL TWO MEMORY BANKING TO IMPROVE PERFORMANCE FOR MULTIPLE SOURCE TRAFFIC AND ENABLE DEEPER PIPELINING OF ACCESSES BY REDUCING BANK STALLS 有权
标题翻译：有效的两级记忆银行，通过减少银行存款，提高多渠道交易的效能和便利的深度管道
公开(公告)号：US20120191915A1
公开(公告)日：2012-07-26
申请号：US13245195
申请日：2011-09-26
申请人： Abhijeet Ashok Chachad , Ramakrishnan Venkatasubramanian
发明人： Abhijeet Ashok Chachad , Ramakrishnan Venkatasubramanian
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： The level two memory of this invention supports coherency data transfers with level one cache and DMA data transfers. The width of DMA transfers is 16 bytes. The width of level one instruction cache transfers is 32 bytes. The width of level one data transfers is 64 bytes. The width of level two allocates is 128 bytes. DMA transfers are interspersed with CPU traffic and have similar requirements of efficient throughput and reduced latency. An additional challenge is that these two data streams (CPU and DMA) require access to the level two memory at the same time. This invention is a banking technique for the level two memory to facilitate efficient data transfers.
摘要翻译：本发明的二级存储器支持一级缓存和DMA数据传输的一致性数据传输。 DMA传输的宽度为16字节。一级指令缓存传输的宽度为32字节。一级数据传输的宽度为64字节。二级分配的宽度为128字节。 DMA传输散布着CPU流量，并且具有类似的有效吞吐量和降低延迟的要求。另外一个挑战是这两个数据流（CPU和DMA）需要同时访问二级存储器。本发明是一种用于二级存储器以促进有效数据传输的银行技术。

12. 发明授权

US08532247B2 Integer and half clock step division digital variable clock divider 有权
标题翻译：整数和半时钟分频数字可变时钟分频器
公开(公告)号：US08532247B2
公开(公告)日：2013-09-10
申请号：US13247265
申请日：2011-09-28
申请人： Ramakrishnan Venkatasubramanian , Anthony Lell , Raguram Damodaran
发明人： Ramakrishnan Venkatasubramanian , Anthony Lell , Raguram Damodaran
IPC分类号： H03K21/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A clock divider divides a high speed input clock signal by an odd, even or fractional divide ratio. The clock divider receives a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates a fractional divide ratio when one and an integral divide ratio when zero. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. The clock divider synthesizes one period of an output clock signal in response to each assertion of the count indicator for a fractional divide ratio and synthesizes one period of the output clock signal in response to two assertions of the count indicator for an integral divide ratio.
摘要翻译：时钟分频器将高速输入时钟信号除以奇数，偶数或分数分频比。时钟分频器接收代表分频比N的除法因子值F，其中N可以是奇数或偶数整数。一个分数指示符表示当零和一个积分分频比为零时的分数分频比。当N为偶数时，每N / 2个输入时钟周期，计数指示器被置位。当N为奇数时，计数指示灯交替显示N / 2个输入时钟周期，然后1 + N / 2个输入时钟周期。时钟分频器响应于分数分频比的计数指示器的每个断言而合成输出时钟信号的一个周期，并响应于积分分频比的计数指示符的两个断言来合成输出时钟信号的一个周期。

13. 发明授权

US08862836B2 Multi-port register file with an input pipelined architecture with asynchronous reads and localized feedback 有权
标题翻译：具有异步读取和本地化反馈的输入流水线架构的多端口寄存器文件
公开(公告)号：US08862836B2
公开(公告)日：2014-10-14
申请号：US13160174
申请日：2011-06-14
申请人： Raguram Damodaran , Ramakrishnan Venkatasubramanian , Naveen Bhoria
发明人： Raguram Damodaran , Ramakrishnan Venkatasubramanian , Naveen Bhoria
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F5/00
CPC分类号： G06F5/00 , G06F9/30141 , G11C8/12
摘要： In an embodiment of the invention, a multi-port register file includes write port inputs (e.g. write address, write enable, data input) that are pipelined and synchronous and read port inputs (e.g. read address) that are asynchronous and are not pipelined. Because the write port inputs are pipelined, they are stored in pipelined registers. When data is written to the multi-port register file, data is first written to the pipelined registers during a first clock cycle. On the next clock cycle, data is read from the pipelined registers and written into memory array registers. Which bits of data from a pipelined synchronous data register are written into the multi-port register file is determined by a pipelined synchronous bit-write register. The output of the pipelined synchronous bit-write register selects which inputs of multiplexers contained in registers in the multi-port register file are stored.
摘要翻译：在本发明的一个实施例中，多端口寄存器文件包括流水线的写入端口输入（例如写入地址，写入使能，数据输入）以及不是流水线的同步和读出端口输入（例如，读取地址）。由于写入端口输入是流水线的，所以它们被存储在流水线寄存器中。当数据写入多端口寄存器文件时，数据将在第一个时钟周期内首先写入流水线寄存器。在下一个时钟周期，数据从流水线寄存器读取并写入存储器阵列寄存器。来自流水线同步数据寄存器的哪些数据位被写入多端口寄存器文件由流水线同步位写入寄存器确定。流水线同步位写入寄存器的输出选择存储多端口寄存器文件中寄存器中包含的多路复用器的哪些输入。

14. 发明申请

US20120324175A1 Multi-Port Register File with an Input Pipelined Architecture with Asynchronous Reads and Localized Feedback 有权
标题翻译：具有异步读取和本地化反馈的输入流水线结构的多端口寄存器文件
公开(公告)号：US20120324175A1
公开(公告)日：2012-12-20
申请号：US13160174
申请日：2011-06-14
申请人： Raguram Damodaran , Ramakrishnan Venkatasubramanian , Naveen Bhoria
发明人： Raguram Damodaran , Ramakrishnan Venkatasubramanian , Naveen Bhoria
IPC分类号： G06F12/00
CPC分类号： G06F5/00 , G06F9/30141 , G11C8/12
摘要： In an embodiment of the invention, a multi-port register file includes write port inputs (e.g. write address, write enable, data input) that are pipelined and synchronous and read port inputs (e.g. read address) that are asynchronous and are not pipelined. Because the write port inputs are pipelined, they are stored in pipelined registers. When data is written to the multi-port register file, data is first written to the pipelined registers during a first clock cycle. On the next clock cycle, data is read from the pipelined registers and written into memory array registers. Which bits of data from a pipelined synchronous data register are written into the multi-port register file is determined by a pipelined synchronous bit-write register. The output of the pipelined synchronous bit-write register selects which inputs of multiplexers contained in registers in the multi-port register file are stored.
摘要翻译：在本发明的一个实施例中，多端口寄存器文件包括流水线的写入端口输入（例如写入地址，写入使能，数据输入）以及不是流水线的同步和读出端口输入（例如，读取地址）。由于写入端口输入是流水线的，所以它们被存储在流水线寄存器中。当数据写入多端口寄存器文件时，数据将在第一个时钟周期内首先写入流水线寄存器。在下一个时钟周期，数据从流水线寄存器读取并写入存储器阵列寄存器。来自流水线同步数据寄存器的哪些数据位被写入多端口寄存器文件由流水线同步位写入寄存器确定。流水线同步位写入寄存器的输出选择存储多端口寄存器文件中寄存器中包含的多路复用器的哪些输入。

15. 发明申请

US20120314833A1 Integer and Half Clock Step Division Digital Variable Clock Divider 有权
标题翻译：整数和半时钟分步数字可变时钟分频器
公开(公告)号：US20120314833A1
公开(公告)日：2012-12-13
申请号：US13247265
申请日：2011-09-28
申请人： Ramakrishnan Venkatasubramanian , Anthony Lell , Raguram Damodaran
发明人： Ramakrishnan Venkatasubramanian , Anthony Lell , Raguram Damodaran
IPC分类号： H03K23/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A clock divider divides a high speed input clock signal by an odd, even or fractional divide ratio. The clock divider receives a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates a fractional divide ratio when one and an integral divide ratio when zero. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. The clock divider synthesizes one period of an output clock signal in response to each assertion of the count indicator for a fractional divide ratio and synthesizes one period of the output clock signal in response to two assertions of the count indicator for an integral divide ratio.
摘要翻译：时钟分频器将高速输入时钟信号除以奇数，偶数或分数分频比。时钟分频器接收代表分频比N的除法因子值F，其中N可以是奇数或偶数整数。一个分数指示符表示当零和一个积分分频比为零时的分数分频比。当N为偶数时，每N / 2个输入时钟周期，计数指示器被置位。当N为奇数时，计数指示灯交替显示N / 2个输入时钟周期，然后1 + N / 2个输入时钟周期。时钟分频器响应于分数分频比的计数指示器的每个断言而合成输出时钟信号的一个周期，并响应于积分分频比的计数指示符的两个断言来合成输出时钟信号的一个周期。

16. 发明授权

US08977878B2 Reducing current leakage in L1 program memory 有权
标题翻译：降低L1程序存储器中的电流泄漏
公开(公告)号：US08977878B2
公开(公告)日：2015-03-10
申请号：US13111617
申请日：2011-05-19
申请人： Ramakrishnan Venkatasubramanian , Hung Vi Ong
发明人： Ramakrishnan Venkatasubramanian , Hung Vi Ong
IPC分类号： G06F1/32 , G06F1/00 , G06F1/26 , G06F13/00 , G11C5/14
CPC分类号： G06F1/3225 , G06F1/3275 , G11C5/148 , Y02D10/13 , Y02D10/14
摘要： An embodiment of the invention provides a method for decreasing power in an L1 program memory of a multi-level memory system. The power is decreased by enabling a sleep mode in the L1 program memory. The sleep mode determines when the L1 program memory will not be accessed for a period of time. When it is determined that the L1 program memory will not be accessed for a period of time, the voltage applied to the memory array is reduced. When it is determined that the L1 program memory will be accessed, the voltage applied to the memory array is increased.
摘要翻译：本发明的实施例提供了一种用于降低多级存储器系统的L1程序存储器中的功率的方法。通过在L1程序存储器中启用睡眠模式来降低功耗。睡眠模式确定L1程序存储器何时不被访问一段时间。当确定L1程序存储器将不被访问一段时间时，施加到存储器阵列的电压减小。当确定将访问L1程序存储器时，施加到存储器阵列的电压增加。

17. 发明申请

US20120297225A1 Reducing Current Leakage in L1 Program Memory 有权
标题翻译：减少L1程序存储器中的电流泄漏
公开(公告)号：US20120297225A1
公开(公告)日：2012-11-22
申请号：US13111617
申请日：2011-05-19
申请人： Ramakrishnan Venkatasubramanian , Hung Vi Ong
发明人： Ramakrishnan Venkatasubramanian , Hung Vi Ong
IPC分类号： G06F1/32
CPC分类号： G06F1/3225 , G06F1/3275 , G11C5/148 , Y02D10/13 , Y02D10/14
摘要： An embodiment of the invention provides a method for decreasing power in an L1 program memory of a multi-level memory system. The power is decreased by enabling a sleep mode in the L1 program memory. The sleep mode determines when the L1 program memory will not be accessed for a period of time. When it is determined that the L1 program memory will not be accessed for a period of time, the voltage applied to the memory array is reduced. When it is determined that the L1 program memory will be accessed, the voltage applied to the memory array is increased.
摘要翻译：本发明的实施例提供了一种用于降低多级存储器系统的L1程序存储器中的功率的方法。通过在L1程序存储器中启用睡眠模式来降低功耗。睡眠模式确定L1程序存储器何时不被访问一段时间。当确定L1程序存储器将不被访问一段时间时，施加到存储器阵列的电压减小。当确定将访问L1程序存储器时，施加到存储器阵列的电压增加。

18. 发明授权

US08375265B1 Delay fault testing using distributed clock dividers 有权
标题翻译：使用分布式时钟分频器延迟故障测试
公开(公告)号：US08375265B1
公开(公告)日：2013-02-12
申请号：US13231229
申请日：2011-09-13
申请人： Ramakrishnan Venkatasubramanian , Alan Hales , William Wallace
发明人： Ramakrishnan Venkatasubramanian , Alan Hales , William Wallace
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G01R31/31858
摘要： In an embodiment of the invention, an integrated circuit with several clock domains bank is tested by first disabling a PLL clock and scanning test data into scan chains. Next delay fault testing (DFT) code is transmitted to each distributed clock divider on the integrated circuit. The PLL clock is then enabled to the distributed clock dividers. Selected clock dividers generate launch pulses that allow test data to be propagated from the scan chains into circuit blocks in the clock domains. Capture pulses are then generated by selected distributed clock dividers to capture test data coming form the circuit blocks into the scan chains. Next the PLL clock is disabled and the test data is scanned from the scan chains to an on-chip test control circuit.
摘要翻译：在本发明的一个实施例中，通过首先禁用PLL时钟并将测试数据扫描到扫描链中来测试具有多个时钟域组的集成电路。下一个延迟故障测试（DFT）代码被发送到集成电路上的每个分布式时钟分频器。 PLL时钟然后被使能到分布式时钟分频器。选择的时钟分频器产生启动脉冲，允许测试数据从扫描链传播到时钟域中的电路块。捕获脉冲然后由选定的分布式时钟分频器产生，以将来自电路块的测试数据捕获到扫描链中。接下来PLL时钟被禁用，测试数据从扫描链扫描到片上测试控制电路。

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