专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US11934334B2 CCIX port management for PCI express traffic 有权
公开(公告)号：US11934334B2
公开(公告)日：2024-03-19
申请号：US17244182
申请日：2021-04-29
申请人： Arm Limited
发明人： Tushar P Ringe , Mark David Werkheiser , Jamshed Jalal , Sai Kumar Marri , Ashok Kumar Tummala , Rishabh Jain
IPC分类号： G06F13/20 , G06F13/40 , G06F13/42
CPC分类号： G06F13/4221 , G06F13/4068 , G06F13/4027 , G06F2213/0026
摘要： The present disclosure advantageously provides a method and system for transferring data over a chip-to-chip interconnect (CCI). At a request node of a coherent interconnect (CHI) of a first chip, receiving at least one peripheral component interface express (PCIe) transaction from a PCIe master device, the PCIe transaction including a stream identifier; selecting a CCI port of the CHI of the first chip based on the stream identifier of the PCIe transaction; and sending the PCIe transaction to the selected CCI port.

12. 发明申请

US20220350771A1 CCIX Port Management for PCI Express Traffic 有权
公开(公告)号：US20220350771A1
公开(公告)日：2022-11-03
申请号：US17244182
申请日：2021-04-29
申请人： Arm Limited
发明人： Tushar P Ringe , Mark David Werkheiser , Jamshed Jalal , Sai Kumar Marri , Ashok Kumar Tummala , Rishabh Jain
IPC分类号： G06F13/42 , G06F13/40
摘要： The present disclosure advantageously provides a method and system for transferring data over a chip-to-chip interconnect (CCI). At a request node of a coherent interconnect (CHI) of a first chip, receiving at least one peripheral component interface express (PCIe) transaction from a PCIe master device, the PCIe transaction including a stream identifier; selecting a CCI port of the CHI of the first chip based on the stream identifier of the PCIe transaction; and sending the PCIe transaction to the selected CCI port.

13. 发明授权

US11086802B1 Apparatus and method for routing access requests in an interconnect 有权
公开(公告)号：US11086802B1
公开(公告)日：2021-08-10
申请号：US16819566
申请日：2020-03-16
申请人： Arm Limited
发明人： Jamshed Jalal , Tushar P. Ringe , Mark David Werkheiser , Gurunath Ramagiri
IPC分类号： G06F13/364 , G06F13/16 , G06F11/30 , G06F9/30 , G06F13/40
摘要： A technique is provided for routing access requests within an interconnect. An apparatus provides a plurality of requester elements for issuing access requests, and a slave element to be accessed in response to the access requests. An interconnect is used to couple the plurality of requester elements with the slave element, and provides an intermediate element that acts as a point of serialisation to order the access requests issued by the plurality of requester elements via the intermediate element. Communication channels are provided within the interconnect to support communication between each of the requester elements and the intermediate element, and between the intermediate element and the slave element. At least one requester element is a channel selectable requester element, and the interconnect further provides, for each channel selectable requester element, a bypass communication channel to support a direct communication between that channel selectable requester element and the slave element that bypasses the intermediate element. Each channel selectable requester element is then arranged, in the presence of a direct slave access condition, to issue an access request over the bypass communication channel to the slave element without that access request passing via the intermediate element.

14. 发明申请

US20200257647A1 SYSTEM, METHOD AND APPARATUS FOR ENABLING PARTIAL DATA TRANSFERS WITH INDICATORS 审中-公开
公开(公告)号：US20200257647A1
公开(公告)日：2020-08-13
申请号：US16271015
申请日：2019-02-08
申请人： Arm Limited
发明人： Tushar P. Ringe , Jamshed Jalal , Anitha Kona , Mark David Werkheiser
IPC分类号： G06F13/42 , G06F13/20
摘要： A system, apparatus and method for an interface based system that may be composed of a diverse set of blocks with different data bus sizes. These different data bus sizes can be optimized by permitting partial data transfers on the different sized buses.

15. 发明授权

US10725958B1 System, method and apparatus for enabling partial data transfers with indicators 有权
公开(公告)号：US10725958B1
公开(公告)日：2020-07-28
申请号：US16271015
申请日：2019-02-08
申请人： Arm Limited
发明人： Tushar P. Ringe , Jamshed Jalal , Anitha Kona , Mark David Werkheiser
IPC分类号： G06F13/00 , G06F13/42 , G06F13/20
摘要： A system, apparatus and method for an interface based system that may be composed of a diverse set of blocks with different data bus sizes. These different data bus sizes can be optimized by permitting partial data transfers on the different sized buses.

16. 发明授权

US10698825B1 Inter-chip communication in a multi-chip system 有权
公开(公告)号：US10698825B1
公开(公告)日：2020-06-30
申请号：US16299291
申请日：2019-03-12
申请人： Arm Limited
发明人： Gurunath Ramagiri , Ashok Kumar Tummala , Mark David Werkheiser , Jamshed Jalal , Premkishore Shivakumar , Paul Gilbert Meyer
IPC分类号： G06F12/00 , G06F12/0817 , G06F16/901
摘要： In a system-on-chip there is a local interconnect to connect local devices on the chip to one another, a gateway to connect the chip to a remote chip of a plurality of chips in a cache-coherent multi-chip system via an inter-chip interconnect, and a cache-coherent device. The cache-coherent device has a cache-coherency look-up table having entries for shared cache data lines. When a data access request is received via the inter-chip interconnect and the local interconnect a system-unique identifier for a request source of the data access request is generated in dependence on an inter-chip request source identifier used on the inter-chip interconnect and an identifier indicative of the remote chip. The bit-set used to express the system-unique identifier is larger than the bit-set used to express the inter-chip request source identifier. The system-unique identifier is used with respect to the cache-coherency look-up table to perform the cache-coherency actions for the cache line enabling more cache coherent devices to be supported.

17. 发明授权

US10310979B2 Snoop filter for cache coherency in a data processing system 有权
公开(公告)号：US10310979B2
公开(公告)日：2019-06-04
申请号：US16189070
申请日：2018-11-13
申请人： Arm Limited
发明人： Jamshed Jalal , Mark David Werkheiser
IPC分类号： G06F12/0815 , G06F12/0831
摘要： A data processing system, having two or more of processors that access a shared data resource, and method of operation thereof. Data stored in a local cache is marked as being in a ‘UniqueDirty’, ‘SharedDirty’, ‘UniqueClean’, ‘SharedClean’ or ‘Invalid’ state. A snoop filter monitors access by the processors to the shared data resource, and includes snoop filter control logic and a snoop filter cache configured to maintain cache coherency. The snoop filter cache does not identify any local cache that stores the block of data in a ‘SharedDirty’ state, resulting in a smaller snoop filter cache size and simple snoop control logic. The data processing system by be defined by instructions of a Hardware Description Language.

18. 发明公开

US20240273025A1 Data Processing Network with Super Home Node 审中-公开
公开(公告)号：US20240273025A1
公开(公告)日：2024-08-15
申请号：US18109453
申请日：2023-02-14
申请人： Arm Limited
发明人： Wenxuan Zhang , Jamshed Jalal , Mark David Werkheiser , Sakshi Verma , Ritukar Khanna , Devi Sravanthi Yalamarthy , Gurunath Ramagiri , Mukesh Patel , Tushar P Ringe
IPC分类号： G06F12/0831 , G06F12/0871
CPC分类号： G06F12/0833 , G06F12/0871
摘要： A super home node of a first chip of a multi-chip data processing system manages coherence for both local and remote cache lines accessed by local caching agents and local cache lines accessed by caching agents of one or more second chips. Both local and remote cache lines are stored in a shared cache, and requests are stored in shared point-of-coherency queue. An entry in a snoop filter table of the super home node includes a presence vector that indicates the presence of a remote cache line at specific caching agents of the first chip or the presence of a local cache line at specific caching agents of the first chip and any caching agent of the second chip. All caching agents of the second chip are represented as a single caching agent in the presence vector.

19. 发明授权

US11431649B1 Interconnect resource allocation 有权
公开(公告)号：US11431649B1
公开(公告)日：2022-08-30
申请号：US17214028
申请日：2021-03-26
申请人： Arm Limited
发明人： Mukesh Patel , Jamshed Jalal , Gurunath Ramagiri , Tushar P Ringe , Mark David Werkheiser
IPC分类号： G06F13/20 , G06F13/42 , G06F12/0888 , G06F15/173 , H04L47/80 , H04L47/78 , H04L47/62 , H04L47/762
摘要： The present disclosure advantageously provides a method and system for allocating shared resources for an interconnect. A request is received at a home node from a request node over an interconnect, where the request represents a beginning of a transaction with a resource in communication with the home node, and the request has a traffic class defined by a user-configurable mapping based on one or more transaction attributes. The traffic class of the request is determined. A resource capability for the traffic class is determined based on user configurable traffic class-based resource capability data. Whether a home node transaction table has an available entry for the request is determined based on the resource capability for the traffic class.

20. 发明授权

US11256646B2 Apparatus and method for handling ordered transactions 有权
公开(公告)号：US11256646B2
公开(公告)日：2022-02-22
申请号：US16685082
申请日：2019-11-15
申请人： Arm Limited
发明人： Tushar P Ringe , Jamshed Jalal , Gurunath Ramagiri , Ashok Kumar Tummala , Mark David Werkheiser
IPC分类号： G06F13/40 , G06F9/46
摘要： An apparatus and method are provided for handling ordered transactions. The apparatus has a plurality of completer elements to process transactions, a requester element to issue a sequence of ordered transactions, and an interconnect providing, for each completer element, a communication channel between that completer element and the requester element for transfer of signals between that completer element and the requester element in either direction. A given completer element that is processing a given transaction in the sequence is arranged to issue a response signal to the requester element over its associated communication channel that comprises an ordered channel indication to identify whether the associated communication channel has an ordered channel property. The ordered channel property guarantees that processing of transactions issued by the requester element over the associated communication channel in a given order will be completed by the given completer element in the same given order. The requester element is then responsive to the ordered channel indication to control timing of issuance from the requester element of at least one signal relating to one or more transactions after the given transaction in the sequence. By such an approach, the ordering flow adopted for ordered transactions can be varied by the requester element in dependence on the presence or absence of an ordered channel, whilst enabling interconnect-agnostic requester element designs to be utilised.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式