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11. 发明授权

US5442144A Multilayered circuit board 失效
标题翻译：多层电路板
公开(公告)号：US5442144A
公开(公告)日：1995-08-15
申请号：US298707
申请日：1994-08-31
申请人： William T. Chen , Thomas P. Gall , James R. Wilcox , Tien Y. Wu
发明人： William T. Chen , Thomas P. Gall , James R. Wilcox , Tien Y. Wu
IPC分类号： H05K3/32 , H05K3/46 , H05K1/00
CPC分类号： H05K3/4632 , H05K3/462 , H05K2201/0129 , H05K2201/015 , H05K2201/09536 , H05K2201/096 , H05K3/328 , Y10T29/49126 , Y10T29/49165
摘要： A method of making a multilayered circuit board wherein at least two layered subassemblies, each comprising a dielectric layer and at least one conductive layer therein, are bonded together. Each subassembly includes a through-hole extending therethrough which is aligned with a respective through-hole of the other prior to bonding. The subassemblies are compressed at a predetermined pressure (e.g., 300 psi) and then heated to a first temperature (e.g., 300.degree. C.) for an established time period, resulting in formation of a bond between the two through-holes. The resulting alloy formed from this bond possesses a melting point significantly greater than that of the subassembly dielectric (e.g., PTFE). Following this time period, the compressed subassemblies are heated to an even greater temperature (e.g., 380.degree. C.), again for an established time period, to assure dielectric flow. The subassembly is then cooled and the pressure removed. The method possesses two significant features: (1) effective engagement between respective pairs of through-holes in the compressed subassemblies; and (2) prevention of dielectric incursion within the bond formed between the respective pairs of through-holes, which incursion could adversely affect the electrical connection therebetween.
摘要翻译：一种制造多层电路板的方法，其中至少两个分层的子组件（每个包括电介质层和至少一个导电层）结合在一起。每个子组件包括贯穿其中的通孔，其在结合之前与相应的通孔对准。子组件在预定压力（例如，300psi）下被压缩，然后被加热到第一温度（例如，300℃）一段既定的时间段，从而在两个通孔之间形成一个键。由该键形成的合金具有显着大于组件电介质（例如PTFE）的熔点。在该时间段之后，将压缩的子组件再次加热到甚至更高的温度（例如380℃），以确定电介质流动。然后将组件冷却并除去压力。该方法具有两个重要特征：（1）压缩子组件中各对通孔之间的有效啮合; 和（2）防止在相应的成对的通孔之间形成的接合中的电介质侵入，这种侵入可能不利地影响它们之间的电连接。

12. 发明授权

US5359767A Method of making multilayered circuit board 失效
标题翻译：制造多层电路板的方法
公开(公告)号：US5359767A
公开(公告)日：1994-11-01
申请号：US112499
申请日：1993-08-26
申请人： William T. Chen , Thomas P. Gall , James R. Wilcox , Tien Y. Wu
发明人： William T. Chen , Thomas P. Gall , James R. Wilcox , Tien Y. Wu
IPC分类号： H05K3/32 , H05K3/46 , H05K3/36
CPC分类号： H05K3/4632 , H05K3/462 , H05K2201/0129 , H05K2201/015 , H05K2201/09536 , H05K2201/096 , H05K3/328 , Y10T29/49126 , Y10T29/49165
摘要： A method of making a multilayered circuit board wherein at least two layered subassemblies, each comprising a dielectric layer and at least one conductive layer therein, are bonded together. Each subassembly includes a through-hole extending therethrough which is aligned with a respective through-hole of the other prior to bonding. The subassemblies are compressed at a predetermined pressure (e.g., 300 psi) and then heated to a first temperature (e.g., 300.degree. C.) for an established time period, resulting in formation of a bond between the two through-holes. The resulting alloy formed from this bond possesses a melting point significantly greater than that of the subassembly dielectric (e.g., PTFE). Following this time period, the compressed subassemblies are heated to an even greater temperature (e.g., 380.degree. C.), again for an established time period, to assure dielectric flow. The subassembly is then cooled and the pressure removed. The method possesses two significant features: (1) effective engagement between respective pairs of through-holes in the compressed subassemblies; and (2) prevention of dielectric incursion within the bond formed between the respective pairs of through-holes, which incursion could adversely affect the electrical connection therebetween.
摘要翻译：一种制造多层电路板的方法，其中至少两个分层的子组件（每个包括电介质层和至少一个导电层）结合在一起。每个子组件包括贯穿其中的通孔，其在结合之前与相应的通孔对准。子组件在预定压力（例如，300psi）下被压缩，然后被加热到第一温度（例如，300℃）一段既定的时间段，从而在两个通孔之间形成一个键。由该键形成的合金具有显着大于组件电介质（例如PTFE）的熔点。在该时间段之后，将压缩的子组件再次加热到甚至更高的温度（例如380℃），以确定电介质流动。然后将组件冷却并除去压力。该方法具有两个重要特征：（1）压缩子组件中各对通孔之间的有效啮合; 和（2）防止在相应的成对的通孔之间形成的接合中的电介质侵入，这种侵入可能不利地影响它们之间的电连接。

13. 发明授权

US08399776B2 Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package 有权
标题翻译：具有单一图案化金属层的基板和应用基板的封装以及基板和封装的制造方法
公开(公告)号：US08399776B2
公开(公告)日：2013-03-19
申请号：US12562950
申请日：2009-09-18
申请人： Bernd Karl Appelt , William T Chen , Calvin Cheung , Shih-Fu Huang , Yuan-Chang Su , Chia-Cheng Chen , Ta-Chun Lee
发明人： Bernd Karl Appelt , William T Chen , Calvin Cheung , Shih-Fu Huang , Yuan-Chang Su , Chia-Cheng Chen , Ta-Chun Lee
IPC分类号： H05K1/09
CPC分类号： H01L23/49827 , H01L21/486 , H01L21/6835 , H01L23/3121 , H01L23/498 , H01L24/12 , H01L24/16 , H01L24/28 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2221/68345 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/29111 , H01L2224/2919 , H01L2224/32057 , H01L2224/32225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/484 , H01L2224/48599 , H01L2224/48699 , H01L2224/73265 , H01L2224/83385 , H01L2224/85439 , H01L2224/85444 , H01L2224/85455 , H01L2224/85664 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/14 , H01L2924/157 , H01L2924/181 , H01L2924/00014 , H01L2924/0665 , H01L2924/00012 , H01L2924/00
摘要： A substrate having single patterned metal layer includes a patterned base having at least a plurality of apertures, the patterned metal layer disposed on the patterned base, and a first surface finish layer. Parts of the lower surface of the patterned metal layer are exposed by the apertures of the patterned base to form a plurality of first contact pads for downward electrical connection externally, and parts of the upper surface of the patterned metal layer function as a plurality of second contact pads for upward electrical connection externally. The first surface finish layer is disposed at least on one or more surfaces of the second contact pads, and the first surface finish layer is wider than the second contact pad beneath. A package applied with the substrate disclosed herein further comprises at least a die conductively connected to the second contact pads of the substrate.
摘要翻译：具有单一图案化金属层的衬底包括具有至少多个孔的图案化基底，设置在图案化基底上的图案化金属层和第一表面光洁度层。图案化金属层的下表面的部分由图案化基底的孔暴露以形成用于向外电连接的多个第一接触焊盘，并且图案化金属层的上表面的一部分用作多个第二接触垫用于向外电连接。第一表面光洁度层设置在第二接触垫的至少一个或多个表面上，并且第一表面光洁度层比下面的第二接触垫宽。施加有本文公开的衬底的封装还包括至少一个导体连接到衬底的第二接触焊盘的管芯。

14. 发明授权

US06258627B1 Underfill preform interposer for joining chip to substrate 失效
标题翻译：用于将芯片连接到基板的底部填充预成型件插入件
公开(公告)号：US06258627B1
公开(公告)日：2001-07-10
申请号：US09233388
申请日：1999-01-19
申请人： Joseph A. Benenati , William T. Chen , Lisa A. Fanti , Wayne J. Howell , John U. Knickerbocker
发明人： Joseph A. Benenati , William T. Chen , Lisa A. Fanti , Wayne J. Howell , John U. Knickerbocker
IPC分类号： H01L2144
CPC分类号： H01L24/28 , H01L21/563 , H01L24/11 , H01L2224/13099 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83102 , H01L2224/92125 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H05K3/3436 , H05K2201/10378 , H05K2201/10674 , H05K2201/10977 , Y02P70/613 , H01L2924/3512 , H01L2924/00
摘要： An apparatus for and method of minimizing the thermo-mechanical fatigue of flip-chip packages. The interposer of the present invention, preferably comprising an organic polymer such as polyimide, contains apertures having conductive plugs inserted therein for joining a chip to a substrate in an electronic module utilizing flip-chip packaging. The interposer is selected to provide optimum spacing between the chip and substrate having a coefficient of thermal expansion adapted to the thermal cycling temperature extremes of the module components. The interposer may comprise an inner core with two adhesive outer layers which may comprise different materials to promote adhesion at their respective interfaces within a module. Conductive plugs are disposed within the apertures of the interposer comprising of a first and second solder or comprising a conductive plug having top and bottom surfaces coated with a conductive adhesive. Preferably, the first solder is disposed within an interior of the apertures and the second solder is disposed within an exterior of the apertures such that the first solder is between a first portion and a second portion of the second solder. Upon reflow, the second solder is reflowed while the first solder remains solid.
摘要翻译：用于最小化倒装芯片封装的热机械疲劳的装置和方法。本发明的插入物优选包含有机聚合物如聚酰亚胺，其中包含插入其中的导电插塞孔，其中使用倒装芯片封装将芯片连接到电子模块中的基片。选择插入器以在芯片和衬底之间提供适合于模块部件的热循环温度极限的热膨胀系数的最佳间隔。插入器可以包括具有两个粘合剂外层的内芯，其可以包括不同的材料以促进在其模块内的各自界面处的粘附。导电插头设置在插入件的孔内，包括第一和第二焊料或包括具有涂覆有导电粘合剂的顶表面和底表面的导电插塞。优选地，第一焊料设置在孔的内部，并且第二焊料设置在孔的外部内，使得第一焊料位于第二焊料的第一部分和第二部分之间。在回流时，第二焊料回流，而第一焊料保持固体。

15. 发明授权

US06255599B1 Relocating the neutral plane in a PBGA substrate to eliminate chip crack and interfacial delamination 失效
标题翻译：将中性平面重新定位在PBGA衬底中，以消除芯片裂纹和界面分层
公开(公告)号：US06255599B1
公开(公告)日：2001-07-03
申请号：US08912451
申请日：1997-08-18
申请人： Chi Shih Chang , William T. Chen , Ajit Trivedi
发明人： Chi Shih Chang , William T. Chen , Ajit Trivedi
IPC分类号： H05K103
CPC分类号： H01L23/49816 , H01L21/563 , H01L23/49822 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/15311 , H01L2924/3511 , H05K1/0271 , H05K1/112 , H05K3/429 , H05K3/4641 , H05K2201/0191 , H05K2201/0352 , H05K2201/09718 , H05K2201/10734 , H01L2924/00
摘要： The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.
摘要翻译：本发明公开了提高使用底部填充封装的翻盖封装的可靠性的技术。本发明的一个实施例描述了一种通过将封装衬底的中性平面远离其中间平面重新定位来封装倒装芯片的方法和装置。本发明的另一个实施例描述了一种将层压板的层布置在用于PBGA封装中的方法和装置，其根据每层的刚度来布置层压板的层。本发明的另一个实施例描述了一种在封装衬底的底部使用一个或多个冗余互连的倒装芯片的封装方法和装置，其中冗余互连在IC芯片的阴影之内。

16. 发明授权

US06177729B1 Rolling ball connector 失效
标题翻译：滚球连接器
公开(公告)号：US06177729B1
公开(公告)日：2001-01-23
申请号：US09303290
申请日：1999-04-03
申请人： Joseph A. Benenati , Claude L. Bertin , William T. Chen , Thomas E. Dinan , Wayne F. Ellis , Wayne J. Howell , John U. Knickerbocker , Mark V. Pierson , William R. Tonti , Jerzy M. Zalesinski
发明人： Joseph A. Benenati , Claude L. Bertin , William T. Chen , Thomas E. Dinan , Wayne F. Ellis , Wayne J. Howell , John U. Knickerbocker , Mark V. Pierson , William R. Tonti , Jerzy M. Zalesinski
IPC分类号： H01L2348
CPC分类号： H01L24/16 , G01R1/0483 , H01L24/11 , H01L24/12 , H01L24/17 , H01L24/83 , H01L2224/05147 , H01L2224/05155 , H01L2224/05568 , H01L2224/05573 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/11003 , H01L2224/11334 , H01L2224/13099 , H01L2224/13111 , H01L2224/1319 , H01L2224/17051 , H01L2224/2919 , H01L2224/8319 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/10253 , H01L2924/14 , H01L2924/15787 , H01L2924/3025 , H01L2924/351 , H05K1/111 , H05K3/321 , H05K2201/0133 , H05K2201/0212 , H05K2201/0221 , H05K2201/0233 , H05K2201/10234 , H05K2201/10734 , H05K2201/10992 , H05K2203/0307 , Y10T428/12472 , H01L2924/00 , H01L2924/3512 , H01L2924/00014
摘要： An integrated circuit assembly has pads of a chip electrically connected to pads of a substrate with rolling metal balls. A pliable material bonds the balls in movable contact with pads of the chip and substrate. Because the balls are relatively free to move, thermal expansion differences that would ordinarily cause enormous stresses in the attached joints of the prior art, simply cause rolling of the balls of the present invention, avoiding thermal stress altogether. Reliability of the connections is substantially improved as compared with C4 solder bumps, and chips can be safely directly mounted to such substrates as PC boards, despite substantial thermal mismatch.
摘要翻译：集成电路组件具有与滚动金属球电连接到衬底的焊盘的芯片焊盘。柔韧的材料将球与芯片和衬底的焊盘可动地接触。由于球相对自由移动，因此在现有技术的连接接头中通常会引起巨大应力的热膨胀差异简单地导致本发明的滚珠滚动，从而完全避免热应力。与C4焊料凸块相比，连接的可靠性大大提高，尽管存在大量的热失配，芯片可以安全地直接安装到诸如PC板的基板上。

17. 发明授权

US5959348A Construction of PBGA substrate for flip chip packing 失效
标题翻译：用于倒装芯片封装的PBGA基板的构造
公开(公告)号：US5959348A
公开(公告)日：1999-09-28
申请号：US912271
申请日：1997-08-18
申请人： Chi Shih Chang , William T. Chen , Ajit Trivedi
发明人： Chi Shih Chang , William T. Chen , Ajit Trivedi
IPC分类号： H01L21/56 , H01L23/00 , H01L23/498 , H05K1/02 , H05K3/34 , H01L25/053 , H01L23/12 , H01L23/14
CPC分类号： H01L23/562 , H01L21/563 , H01L23/49827 , H05K1/0271 , H05K3/4688 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/3511 , H05K2201/0979 , H05K2201/10674 , H05K2201/10734 , H05K3/3436
摘要： The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.
摘要翻译：本发明公开了提高使用底部填充封装的翻盖封装的可靠性的技术。本发明的一个实施例描述了一种通过将封装衬底的中性平面远离其中间平面重新定位来封装倒装芯片的方法和装置。本发明的另一个实施例描述了一种将层压板的层布置在用于PBGA封装中的方法和装置，其根据每层的刚度来布置层压板的层。本发明的另一个实施例描述了一种在封装衬底的底部使用一个或多个冗余互连的倒装芯片的封装方法和装置，其中冗余互连在IC芯片的阴影之内。

18. 发明授权

US5758979A Printer cartridge ribbon inking system 失效
标题翻译：打印机墨盒墨带系统
公开(公告)号：US5758979A
公开(公告)日：1998-06-02
申请号：US741533
申请日：1996-10-31
申请人： William T. Chen
发明人： William T. Chen
IPC分类号： B41J31/16
CPC分类号： B41J31/16
摘要： The inking mechanism of the present invention comprises one or more free-floating inking rollers which rotate within the housing of a printer cartridge between the inking brushes and the printer ribbon. While the rotation of the inking rollers is unlimited, the inking rollers are trapped between the inking brushes, the ribbon and the housing thereby limiting their freedom of movement. The free-floating aspect of the inking rollers provides a desirable pumping action against the inking brushes and the use of the inking brush, the ribbon, and the housing to trap the inking rollers eliminates the need for additional support structure.
摘要翻译：本发明的着墨机构包括一个或多个自由浮动的上墨辊，其在打印墨盒的壳体内在墨水刷和打印机色带之间旋转。当上墨辊的旋转是不受限制的时，上墨辊被夹在着墨刷，色带和外壳之间，从而限制了它们的移动自由度。上墨辊的自由浮动方面提供了对着墨刷的期望的泵送作用，并且使用上墨刷，色带和外壳以捕获上墨辊而不需要额外的支撑结构。

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