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11. 发明授权

US06306760B1 Method of forming a self-aligned contact hole on a semiconductor wafer 失效
标题翻译：在半导体晶片上形成自对准接触孔的方法
公开(公告)号：US06306760B1
公开(公告)日：2001-10-23
申请号：US09457327
申请日：1999-12-09
申请人： Hsin-Tuei Hsu , Yuang-Chang Lin , Wen-Jeng Lin
发明人： Hsin-Tuei Hsu , Yuang-Chang Lin , Wen-Jeng Lin
IPC分类号： H01L21265
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10894
摘要： The present invention relates to a method of forming a self-aligned contact hole on a semiconductor wafer. The semiconductor wafer comprises a substrate, an array area and a periphery area. The array area comprises a first gate electrode and a second gate electrode adjacent to the first gate electrode. The periphery area comprises at least a third gate electrode. A first doped area is formed over each of two opposite sides of each gate electrode. A first spacer is formed on a wall of each of the two opposite sides of the third gate electrode in the periphery area. Then, a second spacer is formed on a wall of each of the two opposite sides of the first and second gate electrodes in the array area. The first spacers are thicker than the second spacers, and the second spacers between the first and second gate electrodes are internal walls of a self-aligned contact hole between the first and second gate electrodes.
摘要翻译：本发明涉及在半导体晶片上形成自对准接触孔的方法。半导体晶片包括基板，阵列区域和周边区域。阵列区域包括与第一栅电极相邻的第一栅电极和第二栅电极。外围区域包括至少第三栅电极。在每个栅电极的两个相对侧的每一个上形成第一掺杂区。第一间隔件形成在周边区域中的第三栅电极的两个相对侧的每个的壁上。然后，在阵列区域中的第一和第二栅电极的两个相对侧的每一个的壁上形成第二间隔物。第一间隔物比第二间隔物厚，并且第一和第二栅电极之间的第二间隔物是第一和第二栅电极之间的自对准接触孔的内壁。

12. 发明授权

US06281134B1 Method for combining logic circuit and capacitor 有权
标题翻译：逻辑电路和电容组合的方法
公开(公告)号：US06281134B1
公开(公告)日：2001-08-28
申请号：US09425603
申请日：1999-10-22
申请人： Wen-Kuan Yeh , Wen-Jeng Lin
发明人： Wen-Kuan Yeh , Wen-Jeng Lin
IPC分类号： H01L213065
CPC分类号： H01L28/40 , H01L21/76807 , H01L27/0629 , H01L28/60
摘要： A method for forming combining a logic circuit and a capacitor of a passive element is disclosed. The method includes the following steps. First, a semiconductor wafer having a first dielectric layer and a first contact is provided. A first metal layer is formed on the first contact and around an estimated area. A second dielectric layer is formed on the first metal layer and the first dielectric layer. The second dielectric layer is formed on the first metal layer and the first dielectric layer. The second metal is formed on areas of the metal layer of the estimated areas. The third dielectric layer is formed on the second metal layer and the second dielectric layer. The fourth dielectric layer is formed on the third dielectric layer. The fifth dielectric layer is formed on the fourth dielectric layer. Sequentially the fifth dielectric layer, the fourth dielectric layer, the third dielectric layer, and the second dielectric layer are all etched.
摘要翻译：公开了一种用于形成组合无源元件的逻辑电路和电容器的方法。该方法包括以下步骤。首先，提供具有第一电介质层和第一触点的半导体晶片。第一金属层形成在第一接触件上并且围绕估计区域。在第一金属层和第一介电层上形成第二电介质层。第二电介质层形成在第一金属层和第一电介质层上。第二金属形成在估计区域的金属层的区域上。第三电介质层形成在第二金属层和第二电介质层上。第四电介质层形成在第三电介质层上。第五电介质层形成在第四电介质层上。顺序地，第五介电层，第四电介质层，第三电介质层和第二电介质层都被蚀刻。

13. 发明授权

US5519108A Catalytic compositions containing tetrabutyl titanate and a mixture of cocatalysts for the preparation of poly(butylene terephthalate) 失效
标题翻译：包含钛酸四丁酯和用于制备聚对苯二甲酸丁二醇酯的助催化剂混合物的催化组合物
公开(公告)号：US5519108A
公开(公告)日：1996-05-21
申请号：US481114
申请日：1995-06-07
申请人： Wu-Bin Yuo , Chien-Shiun Liao , Wen-Jeng Lin , Cheng Yeh , Yu-Shan Chao , Li-Kuel Lin
发明人： Wu-Bin Yuo , Chien-Shiun Liao , Wen-Jeng Lin , Cheng Yeh , Yu-Shan Chao , Li-Kuel Lin
IPC分类号： C08G63/82 , C08G63/02
CPC分类号： C08G63/82
摘要： A catalyst composition for use in the preparation of poly(butylene terephthalate) from dimethyl terephthalate, comprising: (a) a titanium compound primary catalyst, from about 0.0005 PHR to about 5 PHR; (b) a first co-catalyst containing at least one of Zn, Co, Mn, Mg, Ca, or Pb series compounds, between about 0.0001 PHR and 5 PHR; and (c) a second co-catalyst containing an alkali metal phosphate, an alkali metal phosphite, an alkali hypophosphite, or an alkali metal polyphosphate between about 0.0001 PHR and 5 PHR; wherein PHR represents parts of the primary catalyst or the co-catalyst per one hundred parts, by weight, of dimethyl terephthalate. Preferred titanium compounds include tetrabutyl titanate or tetra(isopropyl)titanate. Preferred metal compounds for use as first co-catalyst are metal acetates. The alkali metal phosphate can be a phosphate salt containing one, two, or three metal groups; and the alkali metal phosphite can be a phosphite salt containing one or two metal groups. The alkali metal hypophosphite can be a hypophosphite salt containing any number of alkali metal groups. The alkali metal polyphosphate can be a polyphosphate salt containing one, two, three, four, or five alkali metal groups. With this catalyst composition, the rate of polycondensation was increased by 40 percent or more. The catalyst composition is also effective in the preparation of poly(butylene terephthalate) from terephthalic acid.
摘要翻译：一种用于从对苯二甲酸二甲酯制备聚（对苯二甲酸丁二醇酯）的催化剂组合物，包括：（a）钛化合物一次催化剂，约0.0005PHR至约5PHR; （b）含有Zn，Co，Mn，Mg，Ca或Pb系化合物中的至少一种的第一助催化剂，约0.0001PHR和5PHR之间; 和（c）含有约0.0001PHR与5PHR之间的碱金属磷酸盐，碱金属亚磷酸盐，碱性次磷酸盐或碱金属多磷酸盐的第二助催化剂; 其中PHR代表每100重量份对苯二甲酸二甲酯的主要催化剂或助催化剂的部分。优选的钛化合物包括钛酸四丁酯或钛酸四（异丙基）酯。用作第一助催化剂的优选金属化合物是金属乙酸盐。碱金属磷酸盐可以是含有一个，两个或三个金属基团的磷酸盐; 碱金属亚磷酸盐可以是含有一个或两个金属基团的亚磷酸盐。碱金属次磷酸盐可以是含有任何碱金属基团的次亚磷酸盐。碱金属多磷酸盐可以是含有一个，两个，三个，四个或五个碱金属基团的多磷酸盐。使用该催化剂组合物，缩聚率提高了40％以上。催化剂组合物在从对苯二甲酸制备聚对苯二甲酸丁二醇酯时也是有效的。

14. 发明授权

US07638390B2 Manufacturing method of static random access memory 有权
标题翻译：静态随机存取存储器的制造方法
公开(公告)号：US07638390B2
公开(公告)日：2009-12-29
申请号：US11852185
申请日：2007-09-07
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.
摘要翻译：至少包括衬底，晶体管，上电极和电容器电介质层的静态随机存取存储器（SRAM）单元结构。在衬底中设置器件隔离结构以限定有源区。活动区域有一个开口。晶体管设置在衬底的有源区上。晶体管的源极区域靠近开口。将上电极设置在开口上方，使得开口完全充满。电容器介电层设置在上电极和衬底之间。

15. 发明授权

US07144777B2 Non-volatile memory and manufacturing method thereof 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US07144777B2
公开(公告)日：2006-12-05
申请号：US11066994
申请日：2005-02-25
申请人： Tzung-Han Lee , Wen-Jeng Lin , Kuang-Pi Lee , Blue Larn
发明人： Tzung-Han Lee , Wen-Jeng Lin , Kuang-Pi Lee , Blue Larn
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L29/6653
摘要： A non-volatile memory comprising a substrate, a stacked gate structure, a conductive spacer, an oxide/nitride/oxide layer, buried doping regions, a control gate and an insulating layer. The stacked gate structure is disposed on the substrate. The stacked gate structure comprises a gate dielectric layer, a select gate and a cap layer. The conductive spacer is disposed on the sidewalls of the stacked gate structure. The oxide/nitride/oxide layer is disposed between the conductive spacer and the stacked gate structure and between the conductive spacer and the substrate. The buried doping regions are disposed in the substrate outside the conductive spacer on each side of the stacked gate structure. The control gate is disposed over the stacked gate structure and electrically connected to the conductive spacer. The insulating layer is disposed between the buried doping layer and the control gate.
摘要翻译：包括衬底，堆叠栅极结构，导电间隔物，氧化物/氮化物/氧化物层，掩埋掺杂区域，控制栅极和绝缘层的非易失性存储器。层叠的栅极结构设置在基板上。堆叠栅极结构包括栅极介电层，选择栅极和盖层。导电间隔物设置在堆叠栅结构的侧壁上。氧化物/氮化物/氧化物层设置在导电间隔物和层叠栅极结构之间以及导电间隔物和衬底之间。掩埋掺杂区域设置在层叠栅极结构的每一侧上的导电间隔物外部的衬底中。控制栅极设置在堆叠的栅极结构上并电连接到导电间隔物。绝缘层设置在掩埋掺杂层和控制栅之间。

16. 发明申请

US20060202247A1 SRAM cell structure and manufacturing method thereof 有权
标题翻译： SRAM单元结构及其制造方法
公开(公告)号：US20060202247A1
公开(公告)日：2006-09-14
申请号：US11416699
申请日：2006-05-02
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
IPC分类号： H01L29/94
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.
摘要翻译：至少包括衬底，晶体管，上电极和电容器电介质层的静态随机存取存储器（SRAM）单元结构。在衬底中设置器件隔离结构以限定有源区。活动区域有一个开口。晶体管设置在衬底的有源区上。晶体管的源极区域靠近开口。将上电极设置在开口上方，使得开口完全充满。电容器介电层设置在上电极和衬底之间。

17. 发明申请

US20060197132A1 Sram cell structure and manufacturing method thereof 有权
标题翻译： Sram单元结构及其制造方法
公开(公告)号：US20060197132A1
公开(公告)日：2006-09-07
申请号：US11416925
申请日：2006-05-02
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
IPC分类号： H01L29/94
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.
摘要翻译：至少包括衬底，晶体管，上电极和电容器介电层的静态随机存取存储器（SRAM）单元结构。在衬底中设置器件隔离结构以限定有源区。活动区域有一个开口。晶体管设置在衬底的有源区上。晶体管的源极区域靠近开口。将上电极设置在开口上方，使得开口完全充满。电容器介电层设置在上电极和衬底之间。

18. 发明授权

US06238958B1 Method for forming a transistor with reduced source/drain series resistance 失效
标题翻译：用于形成具有降低的源极/漏极串联电阻的晶体管的方法
公开(公告)号：US06238958B1
公开(公告)日：2001-05-29
申请号：US09477109
申请日：1999-12-31
申请人： Kirk Hsu , Yung-Chang Lin , Wen-Jeng Lin
发明人： Kirk Hsu , Yung-Chang Lin , Wen-Jeng Lin
IPC分类号： H01L2184
CPC分类号： H01L29/665 , H01L29/41775 , H01L29/41783
摘要： A method for forming a transistor in integrated circuits is disclosed. The method includes the following steps. A substrate is first provided. An insulating layer is then formed on the substrate. A conductor layer is formed on the insulating layer. Subsequently, a patterned photoresist layer is formed on the conductor layer. Next, an etch process is used to etch the conductor layer which has a sidewall. The patterned photoresist layer is then removed. After forming a liner layer on the sidewall of the conductor layer, a lightly doped drain is formed on and in the substrate. Then, a spacer is formed on the liner layer. Thereafter, a proper process is used to introduce ions into the lightly doped drain, and then a source/drain region is completed. The steps with follow include annealing the source/drain region and removing the spacer. Subsequently, an epi-silicon layer is formed on the lightly doped drain region, the source/drain region and the top surface of the conductor layer. Finally, the epi-silicon layer is treated with a salicidation process to form a salicide layer.
摘要翻译：公开了一种在集成电路中形成晶体管的方法。该方法包括以下步骤。首先提供基板。然后在衬底上形成绝缘层。在绝缘层上形成导体层。随后，在导体层上形成图案化的光致抗蚀剂层。接下来，使用蚀刻工艺来蚀刻具有侧壁的导体层。然后去除图案化的光致抗蚀剂层。在导体层的侧壁上形成衬垫层之后，在衬底上和衬底中形成轻掺杂漏极。然后，在衬垫层上形成间隔物。此后，使用适当的方法将离子引入轻掺杂的漏极中，然后完成源极/漏极区域。随后的步骤包括对源极/漏极区进行退火并去除间隔物。随后，在轻掺杂漏区，导体层的源/漏区和顶表面上形成外延硅层。最后，用硅化物处理外延硅层以形成自对准硅层。

19. 发明授权

US06180514B2 Method for forming interconnect using dual damascene 失效
标题翻译：使用双镶嵌形成互连的方法
公开(公告)号：US06180514B2
公开(公告)日：2001-01-30
申请号：US09438828
申请日：1999-11-12
申请人： Wen-Kuan Yeh , Wen-Jeng Lin
发明人： Wen-Kuan Yeh , Wen-Jeng Lin
IPC分类号： H01L214763
CPC分类号： H01L21/7681 , H01L21/76801 , H01L21/76841 , H01L2221/1036
摘要： A method for forming inter-metal dielectric is disclosed. The method normally includes the following steps. First of all, a semiconductor wafer is provided. Then, forming a first metal layer on a portion of the substrate is carried out. A first dielectric layer is formed on the first metal layer and the substrate. Consequentially a tantalum nitride layer is formed on the first dielectric layer. A first photoresist layer can be formed on the tantalum nitride layer, especially first photoresist layer has a first pattern defining a trench area located over the first metal layer, and has a second pattern defining an etch stop area. The tantalum nitride layer will be etched by the first photoresist layer. A second dielectric layer is formed over the etched tantalum nitride layer and the first dielectric layer. The second photoresist layer can be formed on the second dielectric layer, especially the second photoresist layer has a first pattern substantially aligned with the first pattern of the first photoresist layer, and has a second pattern substantially aligned with the second pattern of the first photoresist layer. Next, etching the second dielectric layer by the second photoresist layer can be achieved, portion of the first dielectric layer over the first metal layer is further etched by the first pattern of the first photoresist layer. Thus trenches are formed in the first dielectric layer and the second dielectric layer. Then the tantalum nitride layer is deposited into the trenches, especially barrier layer is formed on top surface of the trenches. A seed layer is formed on sidewalls of the etched first dielectric layer and the second dielectric layer. Sequentially, the trenches are filled by a second metal layer. Finally, the second metal layer is planarized to expose surface of said second dielectric layer.
摘要翻译：公开了一种用于形成金属间电介质的方法。该方法通常包括以下步骤。首先，提供半导体晶片。然后，在基板的一部分上形成第一金属层。在第一金属层和基板上形成第一电介质层。因此，在第一电介质层上形成氮化钽层。第一光致抗蚀剂层可以形成在氮化钽层上，特别是第一光致抗蚀剂层具有限定位于第一金属层上方的沟槽区域的第一图案，并且具有限定蚀刻停止区域的第二图案。氮化钽层将被第一光致抗蚀剂层蚀刻。在蚀刻的氮化钽层和第一介电层上形成第二电介质层。第二光致抗蚀剂层可以形成在第二介电层上，特别是第二光致抗蚀剂层具有基本上与第一光致抗蚀剂层的第一图案对准的第一图案，并且具有基本上与第一光致抗蚀剂层的第二图案对准的第二图案。接下来，可以实现通过第二光致抗蚀剂层蚀刻第二介电层，第一金属层上的第一介电层的一部分被第一光致抗蚀剂层的第一图案进一步蚀刻。因此，在第一电介质层和第二电介质层中形成沟槽。然后将氮化钽层沉积到沟槽中，特别是在沟槽的顶表面上形成阻挡层。种子层形成在蚀刻的第一介电层和第二介电层的侧壁上。接下来，沟槽由第二金属层填充。最后，第二金属层被平坦化以暴露所述第二电介质层的表面。

20. 发明授权

US5891987A Copolyamide composition with a high glass transition temperature 失效
标题翻译：具有高玻璃化转变温度的共聚酰胺组合物
公开(公告)号：US5891987A
公开(公告)日：1999-04-06
申请号：US559391
申请日：1995-11-15
申请人： Wu-Bin Yuo , Chien-Shiun Liao , Wen-Jeng Lin , Li-Kuei Lin , Tien-San Lee , Szu-Yuan Chan
发明人： Wu-Bin Yuo , Chien-Shiun Liao , Wen-Jeng Lin , Li-Kuei Lin , Tien-San Lee , Szu-Yuan Chan
IPC分类号： B32B27/34 , C08G69/26 , D01F6/80
CPC分类号： D01F6/80 , B32B27/34 , C08G69/265
摘要： A copolyamide composition prepared from hexamethylene diamine and either mixtures of adipic acid and terephthalic acid, or mixtures of adipic acid, terephthalic acid and isophthalic acid, has a melting point below 320.degree. C., a glass transition temperature between 100.degree. C. and 120.degree. C. and physical properties similar to nylon 66.
摘要翻译：由六亚甲基二胺和己二酸和对苯二甲酸的混合物或己二酸，对苯二甲酸和间苯二甲酸的混合物制备的共聚酰胺组合物的熔点低于320℃，玻璃化转变温度在100℃和120℃之间 DEG和物理性能类似尼龙66。

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