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11. 发明申请

US20130159584A1 DATA BUS INVERSION CODING 有权
标题翻译：数据总线反相编码
公开(公告)号：US20130159584A1
公开(公告)日：2013-06-20
申请号：US13330482
申请日：2011-12-19
申请人： Aaron J. Nygren , Anwar Kashem , Bryan Black , James Michael O'Connor , Warren Fritz Kruger
发明人： Aaron J. Nygren , Anwar Kashem , Bryan Black , James Michael O'Connor , Warren Fritz Kruger
IPC分类号： G06F13/28
CPC分类号： G06F13/4273 , Y02D10/14 , Y02D10/151
摘要： Techniques are disclosed relating to data inversion encoding. In one embodiment, an apparatus includes an interface circuit. The interface circuit is configured to perform first and second data bursts that include respective pluralities of data transmissions encoded using an inversion coding scheme. In such an embodiment, the initial data transmission of the second data burst is encoded using the final data transmission of the first data burst. In some embodiments, the first and second data bursts correspond to successive write operations or successive read operations to a memory module from a memory PHY.
摘要翻译：公开了涉及数据反转编码的技术。在一个实施例中，一种装置包括接口电路。接口电路被配置为执行包括使用反转编码方案编码的相应多个数据传输的第一和第二数据突发。在这样的实施例中，使用第一数据突发的最终数据传输对第二数据脉冲串的初始数据传输进行编码。在一些实施例中，第一和第二数据脉冲串对应于来自存储器PHY的存储器模块的连续写操作或连续读操作。

12. 发明授权

US08134569B2 Aperture compression for multiple data streams 有权
标题翻译：多个数据流的孔径压缩
公开(公告)号：US08134569B2
公开(公告)日：2012-03-13
申请号：US11951184
申请日：2007-12-05
申请人： Brian Etscheid , Mark S. Grossman , Warren Fritz Kruger
发明人： Brian Etscheid , Mark S. Grossman , Warren Fritz Kruger
IPC分类号： G06F12/00 , G06F12/02 , G06F13/00
CPC分类号： G09G5/363 , G09G5/39 , G09G2360/06 , G09G2360/12
摘要： A hardware-based aperture compression system permits addressing large memory spaces via a limited bus aperture. Streams are assigned dynamic base addresses (BAR) that are maintained in registers on sources and destinations. Requests for addresses lying between BAR and BAR plus the size of the bus aperture are sent with BAR subtracted off by the source and added back by the destination. Requests for addresses outside that range are handled by transmitting a new, adjusted BAR before sending the address request.
摘要翻译：基于硬件的孔径压缩系统允许通过有限的总线孔径寻址大的存储空间。流分配动态基地址（BAR），它们保存在源和目的地的寄存器中。 BAR和BAR之间的地址请求以及总线孔径的大小被发送，BAR被源减去并被目的地添加回来。在发送地址请求之前，通过发送一个新的调整后的BAR来处理超出该范围的地址的请求。

13. 发明申请

US20110208989A1 Command Protocol for Adjustment of Write Timing Delay 有权
标题翻译：用于调整写时序延迟的命令协议
公开(公告)号：US20110208989A1
公开(公告)日：2011-08-25
申请号：US12846972
申请日：2010-07-30
申请人： Aaron John Nygren , Ming-Ju Edward Lee , Shadi M. Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger , Michael John Litt
发明人： Aaron John Nygren , Ming-Ju Edward Lee , Shadi M. Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger , Michael John Litt
IPC分类号： G06F1/08
CPC分类号： G06F1/14 , G06F1/08 , G06F13/1689
摘要： A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于基于命令协议来调整存储器设备中的写入定时。例如，该方法可以包括启用写时钟数据恢复（WCDR）操作模式。该方法还可以包括在WCDR操作模式和存储器件的另一操作模式期间将WCDR数据从处理单元发送到存储器件。基于WCDR数据中的相移，可以调整数据总线上的信号与写入时钟信号之间的相位差。此外，该方法可以包括基于数据总线上的信号与写入时钟信号之间调整的相位差在数据总线上传送信号。

14. 发明申请

US20110060879A1 SYSTEMS AND METHODS FOR PROCESSING MEMORY REQUESTS 有权
标题翻译：用于处理存储器请求的系统和方法
公开(公告)号：US20110060879A1
公开(公告)日：2011-03-10
申请号：US12878223
申请日：2010-09-09
申请人： Philip J. ROGERS , Warren Fritz Kruger , Mark Hummel , Eric Demers
发明人： Philip J. ROGERS , Warren Fritz Kruger , Mark Hummel , Eric Demers
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F3/14 , G06F12/0835 , G09G5/001 , G09G5/363 , G09G5/393 , G09G2350/00 , G09G2360/121
摘要： A processing system is provided. The processing system includes a first processing unit coupled to a first memory and a second processing unit coupled to a second memory. The second memory comprises a coherent memory and a private memory that is private to the second processing unit.
摘要翻译：提供处理系统。处理系统包括耦合到第一存储器的第一处理单元和耦合到第二存储器的第二处理单元。第二存储器包括对第二处理单元是私有的相干存储器和专用存储器。

15. 发明授权

US08615637B2 Systems and methods for processing memory requests in a multi-processor system using a probe engine 有权
标题翻译：在使用探针引擎的多处理器系统中处理存储器请求的系统和方法
公开(公告)号：US08615637B2
公开(公告)日：2013-12-24
申请号：US12878223
申请日：2010-09-09
申请人： Philip J. Rogers , Warren Fritz Kruger , Mark Hummel , Eric Demers
发明人： Philip J. Rogers , Warren Fritz Kruger , Mark Hummel , Eric Demers
IPC分类号： G06F12/08 , G06F13/368
CPC分类号： G06F3/14 , G06F12/0835 , G09G5/001 , G09G5/363 , G09G5/393 , G09G2350/00 , G09G2360/121
摘要： A processing system is provided. The processing system includes a first processing unit coupled to a first memory and a second processing unit coupled to a second memory. The second memory comprises a coherent memory and a private memory that is private to the second processing unit.
摘要翻译：提供处理系统。处理系统包括耦合到第一存储器的第一处理单元和耦合到第二存储器的第二处理单元。第二存储器包括对第二处理单元是私有的相干存储器和专用存储器。

16. 发明申请

US20130159818A1 Unified Data Masking, Data Poisoning, and Data Bus Inversion Signaling 有权
标题翻译：统一数据屏蔽，数据中断和数据总线反向信令
公开(公告)号：US20130159818A1
公开(公告)日：2013-06-20
申请号：US13325648
申请日：2011-12-14
申请人： James O'Connor , Aaron Nygren , Anwar Kashem , Warren Fritz Kruger , Bryan Black
发明人： James O'Connor , Aaron Nygren , Anwar Kashem , Warren Fritz Kruger , Bryan Black
IPC分类号： G06F11/07
CPC分类号： G06F13/4239 , Y02D10/14 , Y02D10/151
摘要： Provided herein is a method and system for providing and analyzing unified data signaling that includes setting, or analyzing a state of a single indicator signal, generating or analyzing a data pattern of a plurality of data bits, and signal, or determine, based on the state of the single indicator signal and the pattern of the plurality of data bits, that data bus inversion has been applied to the plurality of data bits or that the plurality of data bits is poisoned.
摘要翻译：本文提供了一种用于提供和分析统一数据信令的方法和系统，其包括设置或分析单个指示符信号的状态，生成或分析多个数据位的数据模式，以及基于单个指示符信号的状态和多个数据位的模式，数据总线反转已被应用于多个数据位或多个数据位被中毒。

17. 发明申请

US20130147821A1 Methods and Systems to Facilitate Operation in Unpinned Memory 有权
标题翻译：方法和系统促进无内存操作
公开(公告)号：US20130147821A1
公开(公告)日：2013-06-13
申请号：US13324443
申请日：2011-12-13
申请人： Warren Fritz Kruger , Philip J. Rogers , Mark Hummel
发明人： Warren Fritz Kruger , Philip J. Rogers , Mark Hummel
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/08
摘要： In an embodiment, a method of processing memory requests in a first processing device is provided. The method includes generating a memory request associated with a memory address located in an unpinned memory space managed by an operating system running on a second processing device; and responsive to a determination that the memory address is not resident in a physical memory, transmitting a message to the second processing device. In response to the message, the operating system controls the second processing device to bring the memory address into the physical memory.
摘要翻译：在一个实施例中，提供了一种在第一处理设备中处理存储器请求的方法。该方法包括：产生与位于由在第二处理设备上运行的操作系统管理的未被固定的存储器空间中的存储器地址相关联的存储器请求; 并且响应于所述存储器地址不驻留在物理存储器中的确定，向第二处理设备发送消息。响应于该消息，操作系统控制第二处理设备以使存储器地址进入物理存储器。

18. 发明授权

US08443225B2 Method and apparatus synchronizing integrated circuit clocks 有权
标题翻译：方法和装置同步集成电路时钟
公开(公告)号：US08443225B2
公开(公告)日：2013-05-14
申请号：US13584560
申请日：2012-08-13
申请人： Aaron Nygren , Ming-Ju Edward Lee , Shadi Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger , Michael Litt
发明人： Aaron Nygren , Ming-Ju Edward Lee , Shadi Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger , Michael Litt
IPC分类号： G06F1/12
CPC分类号： G11C7/1045
摘要： Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.
摘要翻译：本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。根据实施例，在第一IC上提供专用定时引脚。第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。在定时引脚上接收到返回信号。返回信号用于确定是否应由第一个IC调整定时。在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以进行确定。在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

19. 发明申请

US20120303995A1 METHOD AND APPARATUS SYNCHRONIZING INTEGRATED CIRCUIT CLOCKS 有权
标题翻译：方法和装置同步集成电路时钟
公开(公告)号：US20120303995A1
公开(公告)日：2012-11-29
申请号：US13584560
申请日：2012-08-13
申请人： Aaron Nygren , Ming-Ju Edward Lee , Shadi Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger , Michael Litt
发明人： Aaron Nygren , Ming-Ju Edward Lee , Shadi Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger , Michael Litt
IPC分类号： G06F1/12 , G06F1/04
CPC分类号： G11C7/1045
摘要： Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.
摘要翻译：本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。根据实施例，在第一IC上提供专用定时引脚。第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。在定时引脚上接收到返回信号。返回信号用于确定是否应由第一个IC调整定时。在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以进行确定。在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

20. 发明申请

US20110185218A1 Adjustment of Write Timing Based on a Training Signal 有权
标题翻译：基于训练信号调整写时序
公开(公告)号：US20110185218A1
公开(公告)日：2011-07-28
申请号：US12846965
申请日：2010-07-30
申请人： Aaron John Nygren , Ming-Ju Edward Lee , Shadi M. Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger
发明人： Aaron John Nygren , Ming-Ju Edward Lee , Shadi M. Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger
IPC分类号： G06F1/04
CPC分类号： G11C7/1078 , G11C7/1093 , G11C7/222 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/50012 , G11C2207/2254
摘要： A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于基于训练信号调整存储器设备中的写时序。例如，该方法可以包括在训练操作模式下配置存储器设备。该方法还可以包括基于训练信号来确定数据总线上的信号和写入时钟信号之间的写时序窗口。此外，该方法包括基于写时序窗口来调整数据总线上的信号与写入时钟信号之间的相位差。存储器件可以基于调整后的相位差来恢复数据总线上的数据。

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