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    • 15. 发明授权
    • Method and apparatus for summing selected bits from a plurality of machine vectors
    • 用于对来自多个机器向量的所选位进行求和的方法和装置
    • US06363408B1
    • 2002-03-26
    • US09183084
    • 1998-10-30
    • Umair A. KhanNazar A. Zaidi
    • Umair A. KhanNazar A. Zaidi
    • G06F750
    • G06F7/764G06F7/509
    • An apparatus is provided for adding selected bits. The apparatus includes a hardware device having a plurality of ordered input terminals to receive binary signals for a portion of an ordered set of the selected bits. The hardware device also has a plurality of output terminals to transmit digital signals for a plurality of sums. Each sum adds a set of speculative values of a portion of the selected bits. A method is provided for adding a set of ordered selected logic signals. The method includes producing a set of digital signals for a plurality of sums and selecting one of the digital signals for a sum in response to receiving a signal for a correction vector. Each sum adds a set of speculative values for an ordered set of selected logic signals. The selected sum is equal to a sum of speculative values of the selected logic signals as identified by the correction vector. The method also includes transmitting the selected one of the digital signals to an output terminal.
    • 提供了用于添加所选位的装置。 该装置包括具有多个有序输入端的硬件设备,用于接收所选位的有序集合的一部分的二进制信号。 硬件设备还具有多个输出端子,用于传送多个和的数字信号。 每个和添加一组所选位的一部分的推测值。 提供了一种用于添加一组有序选择的逻辑信号的方法。 该方法包括产生用于多个和的一组数字信号,并且响应于接收到用于校正矢量的信号而选择一个数字信号作为和。 每个和添加一组有选择的逻辑信号的有序集合的推测值。 所选择的和等于由校正矢量识别的所选逻辑信号的推测值之和。 该方法还包括将所选择的一个数字信号发送到输出端。
    • 16. 发明授权
    • Method and apparatus for filtering valid information for downstream processing
    • 用于过滤下游处理有效信息的方法和装置
    • US06292882B1
    • 2001-09-18
    • US09209094
    • 1998-12-10
    • Nazar A. ZaidiUmair A. Khan
    • Nazar A. ZaidiUmair A. Khan
    • G06F900
    • G06F9/3802G06F9/3017
    • In one aspect, the invention includes an apparatus for filtering instructions within a digital system that eliminates the need to physically switch the valid instructions onto consecutive data lines of a buffer. The apparatus includes a filter for filtering instructions within a digital system. The filter includes an address generator capable of generating at least two addresses in response to receiving at least two micro-operations. The filter also includes a logic circuit coupled to the address generator. The logic circuit filters addresses corresponding to valid micro-operations in response to assessing the state of a portion of each of the micro-operations. In a second aspect, the invention includes a method for filtering instructions within a digital system that eliminates the need to physically switch the valid instructions onto consecutive data lines of a buffer. The method includes, generating at least two addresses in response to receiving at least two micro-operations. The method further includes filtering addresses corresponding to valid micro-operations in response to assessing the state of a portion of each of the micro-operations.
    • 在一个方面,本发明包括用于对数字系统内的指令进行滤波的装置,其消除了将有效指令物理地切换到缓冲器的连续数据线上的需要。 该装置包括用于过滤数字系统内的指令的滤波器。 该滤波器包括能够响应于接收至少两个微操作而产生至少两个地址的地址发生器。 滤波器还包括耦合到地址发生器的逻辑电路。 响应于评估每个微操作的一部分的状态,逻辑电路对与有效微操作相对应的地址进行滤波。 在第二方面,本发明包括一种用于过滤数字系统内的指令的方法,该方法消除了将有效指令物理地切换到缓冲器的连续数据线上的需要。 该方法包括响应于接收至少两个微操作而产生至少两个地址。 该方法还包括响应于评估每个微操作的一部分的状态来过滤对应于有效微操作的地址。