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11. 发明申请

US20050189974A1 A MULTI-STAGE DELAY CLOCK GENERATOR 失效
标题翻译：多级延时钟发生器
公开(公告)号：US20050189974A1
公开(公告)日：2005-09-01
申请号：US10708373
申请日：2004-02-26
申请人： Tze-Hsiang Chao
发明人： Tze-Hsiang Chao
IPC分类号： G06F1/06 , G06F1/10 , H03L7/06 , H03L7/081 , H03L7/095
CPC分类号： H03L7/0814 , G06F1/06 , G06F1/10 , H03L7/095
摘要： The present invention provides a multi-stage delay clock generator including: a plurality of delay cells, each delay cell generating a delay signal to a subsequent delay cell in response to a delayed clock signal from a preceding delay cell and a delay control signal where a first delay cell among the plurality of delay cells receives an external clock signal, and each subsequent delay cell comprises a smaller delay step than the current delay cell; a phase detector, responsive to the external clock signal and a feedback clock signal, for generating a lock control signal; an integrator, responsive to the lock control signal, for generating the delay control signal; and a control unit for programming the delay cells.
摘要翻译：本发明提供一种多级延迟时钟发生器，包括：多个延迟单元，每个延迟单元响应于来自前一个延迟单元的延迟时钟信号和延迟控制信号而产生延迟信号给后续延迟单元，其中a 多个延迟单元中的第一延迟单元接收外部时钟信号，并且每个后续延迟单元包括比当前延迟单元更小的延迟步长; 响应于所述外部时钟信号和反馈时钟信号的相位检测器，用于产生锁定控制信号; 响应于所述锁定控制信号的积分器，用于产生所述延迟控制信号; 以及用于对延迟单元进行编程的控制单元。

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